White Papers - FPGA
Understanding electronic IP: common issues and how to find them
Using IP blocks in designs requiring DO-254 compliance is becoming more popular as a way to reduce costs and schedules. However, the use of IP comes with its own problems and pitfalls. A good methodology to better screen this IP before its usage can significantly reduce unexpected problems and lower risk, especially on safety critical designs. The most important soft IP screening technologies are automatic formal check and clock domain crossing analysis. This paper will provide a background explanation of IP, including: what types exist in the market; caveats to their usage; and suggestions to better analyze IP before it is used in a design, thus lowering risk and improving product safety. (Note: This paper does not address IP compliance issues. For more information on that topic, please refer to the DO-254 User Group paper "Use of Intellectual Property (IP) Cores in Airborne Electronic Hardware".
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IP Reuse for FPGA Design
Reusing internal designs and incorporating commercial IP can help you quickly complete designs. However, some of this efficiency is lost if you are spending your design time unraveling this IP in order to discover its completeness and accuracy. This paper discuses a methodology to quickly complete the IP discovery process, enhanced through the use of FPGA Advantage.