FPGA/PLD
Integrated FPGA Design Flow
- Design Creation - Manage, create and analyze complex HDL designs
- Simulation - Simulate complex designs regardless of platform or language
- Synthesis - Advanced synthesis for complex FPGA and ASIC designs
Featured FPGA/PLD Techpubs
Demystifying DO-254
Interest in DO-254 first occurred in Europe and has since spread to the US commercial aircraft industry. If you are being asked about your company's DO-254 direction and compliance, but have been overwhelmed with information on the subject, then this article is for you. This article presents DO-254 for the novice, boiling down the standard, reducing it to its essential points so that you will be ready to respond with confidence, as well as understand its potential impact on your products or services.
Managing Timing Constraints with Precision Synthesis
Managing timing constraints often seems like the painful but necessary evil of FPGA design. But "proper constraints are part of proper FPGA design," and adhering to a constraint methodology is important for implementing a design correctly. With more complex clocking schemes in today's FPGAs and the prevalence of high-speed I/O interfaces, constraint management is even more critical to system design. Without proper timing constraints, violations are not seen and the timing analysis is incomplete, potentially leading to faulty in-circuit operation that is difficult to debug.
DO-254 Compliance: Reducing Project Cost by Avoiding Common Pitfalls
Many folks stumble on very similar issues when they begin their journey towards creating and executing DO-254 compliant design projects. The good news is that each of these issues has solutions. Understanding these common pitfalls, and proactively addressing them before they cost a project time, resource and certification risk, is essential. Some of these common pitfalls, along with advice for addressing them (based on learnings from successful DO-254 programs), are described in this paper.
Technical Events:
- Mixed-Signal Design Capture and Simulation within Mentor's Custom-IC Flow
Oct 7, 2008 - San Jose, CA
- DO-254 Pitfalls and Solutions - Webex Series
Oct 7, 2008 - Online
- Innovations in FPGA Synthesis for Faster Design Closure
Oct 7, 2008 - Online (Europe & North America
Oct 7, 2008 - Online (North America)
- Getting Started with Advanced Verification Techniques
Oct 8, 2008 - Irvine, CA
News and Related Articles
- Mentor Graphics Announces Precision Synthesis Support for New Xilinx Virtex-5 TXT Field Programmable Gate Arrays Sep 23, 2008
- Thales and Mentor Graphics Halve Time-to-Productivity for New Design EngineersMay 27, 2008
- Mentor Graphics Supports Altera’s Stratix IV FPGA Device Family for 40 Nanometer Design ApplicationsMay 19, 2008