Partitioning and Synthesizing ASIC Prototypes using FPGAs
Online Event RegistrationClick Here to Register and View Today!OverviewIf you're designing an ASIC, a respin due to verification errors can result in millions of dollars in cost and schedule overruns. More and more ASIC designers consider prototyping in FPGAs as a way to reduce risk and verify design functionality before committing to silicon. Using Altera FPGAs and Mentor Graphics synthesis tools, you can now fully realize the promised benefits of prototyping and thus ensure that your ASIC designs will work as intended! Duration: 1 hour |