IBD - Structure Assembly & Reuse with Table Based Methods
Overview
Technology, Reuse and HDL Design: Approaches for ASIC or FPGA Designers
To meet the schedules and demands for complex ASIC and FPGA design projects, reusing HDL code as building blocks for new and next generation designs has become a common practice. Since a large volume of code from many designers and projects often exists within a company, the reuse approach seems very practical, but in reality, the reuse task can prove to be very challenging.
Join us for these thirty minute online seminars to learn some practical approaches to design projects, managing the files and artifacts and incorporating methods to improve efficiency and design reuse. The demonstrations are especially useful for engineers that use or are familiar with HDL Designer Series.
Times:
- Asia Pacific – 13:00 Tokyo
- Europe & North America – 15:00 London, 10:00am New York
- North America – 2:00pm San Francisco
Who Should Attend
- Engineering managers
- Project managers
- Engineers and designers
What You Will Learn
As designs grow in complexity, the number of design block interconnects can grow at an alarming rate. While analyzing a pre-existing block for reuse, a designer can become overwhelmed with the sheer number of interconnects associated with a large block and lose the ability to understand the design intent. This presentation will show how HDL Designer offers an effective solution to the challenges of creating and navigating complex RTL design interfaces with the Interface Based Design (IBD) tool feature to significantly aid in understanding the reused HDL code.