FPGA/PLD Industry Articles

2008

Konica Minolta Designs FPGAs Using Behavioral Synthesis  Nov 26

How to raise the RTL abstraction level and design conciseness with SystemVerilog - Part 2  May 15

How to raise the RTL abstraction level and design conciseness with SystemVerilog - Part 1  Apr 30

How To Implement SystemVerilog for FPGA Design  Apr 29

Freedom of Choice is Key for FPGA Design Projects  Mar 10

SystemVerilog is Coming to FPGA Design  Feb 19

Three “I”s of FPGA Design: Iterations, Incremental and Intelligent Design Tools  Jan 22

2007

New Approach to FPGA Physical Synthesis for Ease-of-Use and Wide Device Support  Dec 18

Temento to Delivers Integrated FPGA Hardware Debug Solution for Mentor Graphics Precision Synthesis Customers  Nov 13

Duct Tape, FPGAs, and the Art of Making Great Multi-Purpose Tools  Oct 30

A New Way to Design FPGAs  Sep 11

Top-down DSP design for FPGAs  Sep 05

The Need for Incremental FPGA Synthesis  Aug 11

How to enable Microsoft Office and Visio for RTL design  Jul 18

Accelerating DO-254 for ASIC/FPGA designs  Jun 07

The Need for an FPGA Resource Manager  May 03

The Value of a Complete FPGA Design Flow  May 01

Auspy Development Inc. Joins Mentor Graphics OpenDoor Program  Apr 24

Deterministic Name Generation for Incremental Synthesis  Mar 13

Focusing on Primary ESL Design Solutions  Feb 15

Making FPGA Synthesis Physically Aware  Feb 15

The Importance of Design Analysis in FPGA Synthesis  Feb 15

Getting the most out of ASIC prototyping with FPGAs  Feb 07

Altera Makes Its Advanced Signal Integrity Technology Available Through EDA Partners  Jan 23

2006

Precision is better & at 1/3 price of Synplicity  Dec 14

Mentor offers synthesis support for Stratix III  Nov 08

Enhanced tool suite supports Lattice's 90-nm FPGAs  Oct 26

How to utilize advanced FPGA features without getting locked into an architecture  Oct 18

FPGAs Ride Tools Into ASIC Territory  Sep 28

ASIC Prototyping with FPGAs - YES, Please!  Sep 26

SystemVerilog - The Changing Role of Synthesis (English version)  Sep 04

Should You Reuse RTL?  Jun 06

Time for a Change: Mentor Modernizes the ECO  May 30

The Real Story behind FPGA-Based Quality-of-Results (QoR)  May 09

Temento Systems Announces Tight Integration of DiaLite 4.5 Edition with MENTOR GRAPHICS PRECISION Synthesis  May 08

Blaming the Button  Apr 25

Optimizing DSP functions in advanced FPGA architectures  Jan 25

2005

A practical approach to reusing HDL code in FPGA designs  Dec 28

Mentor, QuickLogic Integrate FPGA Synthesis  Dec 28

QuickLogic and Mentor in OEM agreement on FPGA tools  Dec 27

How to use register retiming to optimize your FPGA designs  Dec 14

FPGA Design Meets the Heisenberg Uncertainty Principle  Nov 05

QuickLogic Lowest-Power FPGAs Supported by Precision Synthesis From Mentor Graphics  Oct 31

A Good Methodology Helps Design Teams Check RTL Code  Oct 27

Preventing the Blame Game  Oct 07

Programmable logic: Understanding the risks in military and aerospace applications  Oct 05

EDA Alert e-Newsletter: Simon Bloch viewpoint on mentor.com  May 10

2004

FPGA Go, Go, Go: Solving the FPGA timing closure challenge for high-speed designs, Chip Design  Jun 01

Head2Head: FPGA Pricing, Chip Design  Jun 01

ModelSim Enables Rapid Prototyping of VeriWave Wireless LAN Test Equipment  May 05

2003

Basics of FPGA Design  Dec 01