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FPGA/PLD Industry Articles

2008

2007

New Approach to FPGA Physical Synthesis for Ease-of-Use and Wide Device Support Dec 18
Temento to Delivers Integrated FPGA Hardware Debug Solution for Mentor Graphics Precision Synthesis Customers Nov 13
Duct Tape, FPGAs, and the Art of Making Great Multi-Purpose Tools Oct 30
A New Way to Design FPGAs Sep 11
Top-down DSP design for FPGAs Sep 05
The Need for Incremental FPGA Synthesis Aug 11
How to enable Microsoft Office and Visio for RTL design Jul 18
Accelerating DO-254 for ASIC/FPGA designs Jun 20
The Need for an FPGA Resource Manager May 03
The Value of a Complete FPGA Design Flow May 01
Auspy Development Inc. Joins Mentor Graphics OpenDoor Program Apr 24
Deterministic Name Generation for Incremental Synthesis Mar 13
Focusing on Primary ESL Design Solutions Feb 15
Making FPGA Synthesis Physically Aware Feb 15
The Importance of Design Analysis in FPGA Synthesis Feb 15
Getting the most out of ASIC prototyping with FPGAs Feb 07
Altera Makes Its Advanced Signal Integrity Technology Available Through EDA Partners Jan 23

2006

Precision is better & at 1/3 price of Synplicity Dec 14
Mentor offers synthesis support for Stratix III Nov 08
Enhanced tool suite supports Lattice's 90-nm FPGAs Oct 26
How to utilize advanced FPGA features without getting locked into an architecture Oct 18
FPGAs Ride Tools Into ASIC Territory Sep 28
ASIC Prototyping with FPGAs - YES, Please! Sep 26
SystemVerilog - The Changing Role of Synthesis (English version) Sep 04
Should You Reuse RTL? Jun 06
Time for a Change: Mentor Modernizes the ECO May 30
The Real Story behind FPGA-Based Quality-of-Results (QoR) May 09
Temento Systems Announces Tight Integration of DiaLite 4.5 Edition with MENTOR GRAPHICS PRECISION Synthesis May 08
Blaming the Button Apr 25
Optimizing DSP functions in advanced FPGA architectures Jan 25

2005

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