Mentor Graphics Unveils Comprehensive Design Tool Flow to Address Challenges of Designing Complex FPGAs
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WILSONVILLE, Ore., May 19, 2003 - Mentor Graphics Corporation (Nasdaq: MENT) today announced a comprehensive FPGA design flow that expands traditional FPGA tools with new technologies to address emerging challenges of complex FPGA designs. The three-part flow, which extends from high-level FPGA design through Printed Circuit Board (PCB) design, includes existing and future technologies for the design and verification of the FPGAs, embedded systems, and PCBs containing FPGAs. The combination of large, complex IP blocks, memories, high speed IO, hard and soft embedded processors and embedded software on a single FPGA, exacerbated by the soaring system gate counts and packaging requirements, taxes the capabilities of traditional design methodologies. The design of these chips requires a new degree of sophistication, characterized by deeper, system-level design, concurrent hardware/software design and verification at all stages of the design process. To avoid a design gap in FPGA solutions, Mentor continues to execute on a strategy to provide integrated tools that continue to address the complexity of new architectures, thereby helping designers preserve the inherent productivity advantages of FPGAs. "Mentor Graphics is the only EDA company with a fully integrated tool solution capable of handling all aspects of FPGA design, from verification and synthesis to embedded software and board layout," said Walden C. Rhines, chairman and CEO of Mentor Graphics. "We are advancing our position in FPGA design by building beachheads around our tools that are de facto standards in their respective markets." "The device complexity of FPGAs continues to increase rapidly with the advent of new architectures," said Simon Bloch, general manager of the FPGA Design Division. "To maintain the design productivity advantage of FPGAs and complement the traditional FPGA design flows, customers are shifting to design approaches that mirror those of ASICs. Mentor Graphics offers the most complete portfolio of products to address the increasing challenges of FPGA designers." The Mentor Graphics? FPGA Design Tool Flow
FPGA Design and Verification Design Creation and Management Synthesis "When using Precision RTL Synthesis tool, a simple synthesis run offers convincing area and timing estimates so that the number of place-and-route runs can be reduced considerably," said Johann Notbauer, technical director, CES Design Services, a business unit of Siemens Program and System Engineering. "Because each place-and-route run can take twelve hours or more for a complex design, this saves valuable time and yields better results." Mentor Graphics continues to expand the Precision Synthesis tool solution to help designers accelerate the lengthy timing closure process by minimizing place-and-route iterations. The physical synthesis technologies provide automated physically aware algorithms that use placement and post-place-and-route timing information for retiming, replication and re-synthesis. This can eliminate lengthy design iterations, multiple place-and-route iterations and floorplanning steps. After automation has done as much as possible, the tool offers designers an interactive environment for manual improvements to further tune designs to achieve faster performance or desired speed grades. General availability of the physical synthesis technology is expected in the second half of 2003. To accommodate the need to design large and complex FPGAs efficiently, the Precision product line is incorporating technologies to raise the level of design abstraction from RTL to C. These new technologies enable designers to quickly trade-off design performance and area by working at the algorithmic level of the design, allowing for rapid exploration and implementation. General availability of the high-level synthesis technology is expected at the end of 2003. Simulation An Integrated FPGA Design Solution Formal Verification Intellectual Property Embedded Software Integration and Development To support these trends, Mentor offers a complete software development suite that includes cross compilers and debuggers in an embedded IDE, closely linked to the NucleusTM RTOS, TCP/IP networking stack and other middleware that has been ported to many of the popular processors used in programmable devices. Both development tools and RTOS have been validated with devices from Altera and Xilinx, including recently announced comprehensive support for Altera's NIOS-based devices. Further announcements on the Nucleus RTOS design kits for FPGA devices will be made throughout 2003. Co-Verification Platform-Based Design PCB System Design and Verification Mentor's FPGA BoardLinkTM product automates the critical time-consuming and error-prone tasks faced by the PCB designer. Schematic symbol generation is automatic, utilizing implementation- specific FPGA signal names from the FPGA Advantage tool, while leveraging corporate PCB library information. The user is given the added option of user-directed symbol fracturing allowing high pin count devices to be broken down into multiple symbols. FPGA pin assignments change typically three times or more during a design phase. The FPGA BoardLink product incorporates these pin assignment changes from the FPGA Advantage design environment with automatic updates to the schematic symbol removing the need to re-wire the PCB schematic. First customer availability is expected in June of 2003. FPGA designs continue to push the high-speed performance envelope with multi-gigabit I/O capability. This capability demands tight integration of timing and signal integrity analysis within the PCB design flow. Mentor Graphics has partnered with Xilinx, Altera and Actel to provide a combination of new analysis capabilities and certified high-speed design kits that FPGA designers need to meet their multi-gigabit design requirements. Mentor Graphics also leads modeling format standardization efforts to support multi-gigabit design requirements. The company is also working with FPGA vendors to implement these standards, ensuring model availability and implementation is seamless for all customers. These modeling extensions dramatically increase the simulation capability and accuracy provided in Mentor's tools, while at the same time reducing the modeling effort for end users. Finally, high-speed design principles and methods represent a new frontier for many FPGA designers. To help solve these new challenges, Mentor is working with the FPGA vendors and supplying signal integrity tools to enable field application engineers to educate their teams on the topics of high-speed design. Availability About Mentor Graphics Mentor Graphics, ModelSim, Seamless, FPGA Advantage and Nucleus are registered trademarks and Precision Synthesis, LeonardoSpectrum, HDL Designer Series, Inventra, Platform Express, and FPGA BoardLink are
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