Mentor Graphics Adds New Design Creation and Management Features for Complex FPGA Design in FPGA Advantage 5.3

Advances to FPGA Advantage 5.3 Include Enhanced Design Creation and Management Features

Wilsonville, OR, July 10, 2002 - - Mentor Graphics Corporation (Nasdaq: MENT) today introduced FPGA Advantage. The FPGA Advantage 5.3 IBD editor solves problems design engineers have with complex interconnect creation. IBD allows complex interconnect structures to be viewed in a compact tabular format. Users can rapidly specify the signal connections and automatically generate the equivalent structural description in VHDL or Verilog. The IBD tabular format also enables design constraints and synthesis properties to be specified and then be propagated to the downstream phases of the design flow.

FPGA Advantage's debugging capabilities have been expanded with version 5.3 to include visualization of text files during interactive simulation debug. These graphical and tabular diagrams of HDL source code enhance HDL simulation and improve design verification productivity.

FPGA Advantage 5.3 provides additional enhancements for FPGA designers, including:

• Ability to add and remove hierarchy levels
• Frames for multiple instance instantiations
• Signal stubs for signal slicing
• Dataflow window X-tracing
• Support for Microsoft

Mentor Graphics continues to extend FPGA Advantage's capabilities to handle the latest device complexities from the FPGA market leaders, said Valerie Rachko, director of marketing, HDL design and FPGA solutions, Mentor Graphics. Mentor is the only EDA tool vendor to offer an integrated FPGA design flow for design creation, debug, simulation and synthesis.

Support for Altera's MegaWizard and LogicLock Programmable Logic Solutions

• FPGA Advantage 5.3 adds Verilog support for Altera
• FPGA Advantage 5.3 continues to offer VHDL and Verilog support for Xilinx

Pricing and Availability

• FPGA Advantage 5.3 is available immediately through the Mentor Graphics

About Mentor Graphics Corporation
Mentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about million and employs approximately 3,500 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site: www.mentor.com .

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Mentor Graphics and FPGA Advantage are registered trademarks of Mentor Graphics Corporation. Interfaced-Based Design and IBD are trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.

For more information, please contact:
Suzanne Graham Mentor Graphics 503.685.7789 suzanne_graham@mentor.com	Jason Khoury Weber Shandwick 415.354.8391 jkhoury@webershandwick.com