Mentor Graphics HDL Designer Series Addresses Critical Design Creation and Management Issues
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WILSONVILLE, Ore., June 30, 2003 - Mentor Graphics Corporation (Nasdaq: MENT) today announced the release of HDL Designer SeriesTM 2003.1, the latest version of the industry-leading environment for the creation, development and management of complex ASIC and FPGA semiconductor designs. HDL Designer Series 2003.1 includes new design management, creation, analysis and documentation capabilities. Mentor Graphics continues to enhance HDL Designer Series to be seamlessly interoperable with its best-in-class design flow, helping customers accelerate and simplify the development of leading-edge ASIC and FPGA designs. "Complexity in all its dimensions, from the number of design files to the growing number of system gates, challenges traditional approaches to semiconductor design," said Valerie Rachko, marketing director, HDL Designer Series, Mentor Graphics. "With version 2003.1, we've added new design creation and management features that enable designers to navigate, organize and edit their designs in the format of their desire. We provide individuals with flexibility while providing organizations with the control to regulate how designs are shared through companies or across generations." A Predictable, Flexible Design Process Minimizes Design Risk Rapid Design Development Improvements Increase Productivity Additional entry methods Include Interface-Based DesignTM (IBDTM), a unique tabular design methodology for rapidly editing structural HDL for large and complex designs, and ModuleWareTM, which generates silicon-vendor-independent logic for a variety of common logic functions. HDL Designer Series 2003.1 also includes intuitive graphical editors, such as block diagrams, state machines, flow charts and truth tables. Practical IP and Design Reuse Powerful and Early Design Analysis Cuts Verification Time Automated Communications for Distributed Design Teams Pricing and Availability HDL Designer Series 2003.1 is included in FPGA Advantage 6.1, also announced today. FPGA Advantage is the EDA industry's most interoperable and flexible design flow for managing FPGA design creation, verification and implementation. For more information, please visit www.mentor.com/fpga-advantage. About Mentor Graphics Mentor Graphics and ModelSim are registered trademarks of Mentor Graphics Corporation. HDL Designer Series, HDL Pilot, HDL Detective, HDL Author, HDL Designer and Debug Detective are trademarks of Mentor Graphics. All other company or product names are the registered trademarks or trademarks of their respective owners. ###
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