Programmable System-on-Chip Devices Take Innovation to the Next Level

Mentor Graphics Corp., 3/1/2003 - The challenges associated with complex semiconductor design have been aided by new programmable logic technologies that offer viable and cost-effective alternatives to hard-coded application-specific integrated circuits (ASICs). In the last 18-months, programmable logic vendors have introduced new platforms with performance benchmarks that rival ASIC designs, without the incurred cost of a $1-million mask set or requirements for minimum volumes. To achieve this high performance, these new platforms contain a large quantity of programmable logic with embedded microprocessor cores, memory and advanced intellectual property (IP). These features provide significant benefits for the designer, such as reduced system development and the flexibility to make changes right up to production. The devices, characterized as programmable system-on-chip (SoC) platforms, represent a dramatic technical breakthrough. However, with all disruptive technologies come new design and verification challenges. These challenges require new and unique remedies.

New Technology Requires Advanced Methodology
The combination of large, complex IP blocks, hard and soft embedded processors and embedded software on a single chip, along with soaring transistor counts, tax the capabilities of traditional design methodologies. The design of these chips requires a new degree of sophistication, characterized by deeper, system-level design, concurrent hardware/software design and verification at all stages of the design process.

When hard or soft microprocessors are embedded on a programmable platform, designers face the difficult challenges associated with embedded software development. Design environments must include software compilers, software debuggers and hardware-connection probe tools that support both hard and soft processor core technologies. New system designs have multiple microprocessors on a board, and the move is toward multiple processors in a single device. To support these trends, software development suites must include compilers, embedded software and a debugger optimized for target processor architectures.

System-level design tools can guide users through hardware and software partitioning, facilitating the attachment of microprocessor cores and blocks of logic to platforms. But with modern programmable logic devices, there is a potentially huge divide between what can be put in the chip versus what can be verified to work. Bridging this gap requires the integration of many pieces of the hardware/software design and verification paradigm: software debugging, event-driven logic simulation and complex IP modeling.

Verification
As the design focus shifts from content creation to the challenges of evaluating, integrating and verifying multiple pre-existing blocks and software components, designers will have to deploy advanced verification tools such as co-verification. Hardware and software must be designed and verified in parallel. Programmable SoCs are so large and complex that re-designs in the future will incur even more significant delays than they already do today.

ASIC designers who use MPU cores such as ARM, MIPS and PowerPC already employ hardware/software co-verification techniques to spot system design issues early in the development cycle. Increasingly, these methodologies will be carried over into field-programmable gate array (FPGA) design.

Traditional simulation methods have also been enhanced to provide new features that add advanced debugging capabilities. With the increase in design sizes, bugs are becoming harder and harder to find and fix. New tools offer graphical debug capabilities to help designers quickly trace design behavior back to the source.

Synthesis
Many synthesis tools look at RTL code on a line-by-line basis and build up the design from low-level gates. With the increase in design size associated with large Programmable SoC devices, this approach becomes extremely time-consuming and does not deliver the highest quality results. New approaches examine the intent of the RTL and build up the architecture of the design from large building blocks. This approach allows users to take full advantage of a new FPGA architecture, detecting architectural signatures and using algorithms optimized to deliver the best results.

New programmable devices have moved into the technology range where accuracy is everything. Rapid timing closure remains an ongoing goal, and achieving this is strained by advanced technology developments, including 0.13 and below silicon technology and wire loads that consume 50 to 70 percent of circuit delay.

Small geometries and the increased role of interconnects in device behavior require new synthesis methods. It becomes far more difficult to predict timing because the interconnect delays are greater than the intrinsic gate delays. To solve new timing issues and guarantee a reliable design, synthesis tools must include timing engines and constraint entry systems designed to handle complex timing analysis.

Other methods for achieving timing closure include physical synthesis. Traditional physical synthesis approaches such as re-writing the RTL, working with the constraints or even floor planning add value, but smarter synthesis algorithms that leverage actual physical data are required to help the designer keep pace with technology advancements and get their products to market faster. Automated algorithms such as re-timing, replication and re-synthesis add value especially when they are re-inforced with placement optimization. After automation has done as much as possible, an interactive environment allows the user to close on those last few signals.

To complete a programmable platform system design requires chip and board design to be conducted in parallel. Concurrent design enables system engineers to synchronize the FPGA with the board, minimizing interconnectivity delay and accelerating system timing closure. Parallel design of the FPGA and the board allows designers to create faster, denser boards and to simulate the whole system.1

Innovation Ahead
Market dynamics are changing as consumerization squeezes project lifecycles down to months rather than years. With shorter product cycles, the flexibility of programmable logic is extremely advantageous.

As FPGAs support limited but widespread products and platforms, design efforts will be more focused. Programmable SoC invites innovation, and it puts complex silicon in the hands of most designers for the first time and it makes available unprecedented system design methodologies.

Innovation — driven by the large user base — will occur rapidly. Therefore, programmable technology will mature at a faster pace than ASICs. Consequently, programmable SoC and its supporting tools will develop quickly. Historically, it took more than 10 years to put the tools in place for the typical ASIC design flow. Adoption of those same tools for FPGA applications is happening much faster. Early ASIC applications have pipe-cleaned the tool flow for hardware/software design and verification, enabling EDA developers to rapidly deploy robust, proven tool flows for designing complex programmable SoC devices.

1In many cases, the programmable device will be used alongside standard microprocessors and DSPs. Models for these processors are also available with Seamless, which scales easily to enable designers to use the same tool for both device and system level co-verification.

Author: Valerie Rachko is the Director of Marketing for HDL design and FPGA solutions at Mentor Graphics Corporation. She has been marketing HDL design products, including HDL Designer Series and FPGA Advantage, for Mentor Graphics since 1990. Prior to joining Mentor Graphics, she worked as an ASIC designer for more than five years. Rachko earned a bachelor's and master's degree in electrical & electronic engineering from Fairleigh Dickinson University and a master's degree in business administration with an emphasis in marketing from Seton Hall University. Mentor Graphics Corporation is located at 8005 SW Boeckman Rd., Wilsonville, OR 97070; (800) 592-2210; www.mentor.com.