Comparison Matrix
| OEM version "Level1" | "Level3 | Insight OPTION to Level1 or Level3 | |
| 1. Synthesis of all FPGA and CPLD to successfully complete even the most challenging of designs | |||
| ¨ Verilog or VHDL RTL Synthesis, Mapping and F.A.S.T. Optimization to create the highest Quality of Results | a | a | |
| ¨ Push button flow available for ease of use | a | a | |
| ¨ TCL Scripting to allow user to automate specific design flows | a | a | |
| ¨ Batch mode available | a | a | |
| ¨ Graphical user Interface | a | a | |
| ¨ Encrypted IP support | a | a | |
| ¨ FSM optimization | a | a | |
| ¨ HDL Source code editor to quickly edit/ adjust your HDL | a | a | |
| ¨ Graphical Constraint Editor for intuitive adjustment of constraints | a | a | |
| ¨ Syntax error cross highlighting for rapid debug | a | a | |
| ¨ Context sensitive HELP | a | a | |
| ¨ RAM, ROM, counter inferencing for optimal design implementation | a | a | |
| ¨ Incorporate vendor/3rd party cores in your synthesized design | a | a | |
| ¨ Accurate Timing Reports (pre and post Place and Route) | a | a | |
| 2. Better Integration and Flow | |||
| ¨ Back end Design flow integration w/ FPGA/CPLD Vendor toolset | a | a | |
| ¨ Pre Place and Route Simulation Flow | a | a | |
| 3. Productivity - For large design teams or complex FPSoC applications | |||
| ¨ Modular design flow w/ Design Hierarchy manipulation | a | ||
| ¨ Design assembly from more than one block | Only during | Before | |
| ¨ Integration w/ FPGA vendor Floorplanning, Place & Route Tools | a | a | |
| ¨ Can assign synthesized cells to physical locations | a | a | |
| 4. Fewer P&R iterations and faster timing closure - Automatically fix problems without re-coding HDL | |||
| ¨ Incremental Optimization of regions that do not meet timing or area requirement | a | ||
| ¨ Optimization across hierarchical boundaries to improve timing | a | ||
| ¨ Don’t touch regions of the design that already work | a | ||
| Fewer P&R iterations and faster timing closure - Catch and correct gross problems before Place & Route ¨ Design Assembly and Hierarchy manipulation ¨ Incremental Optimization of regions that do not work ¨ Leverage accurate post P&R delay info via SDF back-annotation | a a | ||
| Fewer P&R iterations and faster timing closure – Advanced Static Timing Design Analysis / Debug to identify and fix timing problems | |||
| ¨ Timing Analysis through cores | a | ||
| ¨ I/O Pad to register and register to I/O pad timing | a | a | |
| ¨ Cross probing from schematic to RTL | a | ||
| ¨ User-customizable Critical path identification and SEARCH | a | ||
| Fewer P&R iterations and faster timing closure - Intuitive Schematic viewing, with easy design navigation and debug | |||
| ¨ Schematic viewer and navigation | a | ||
| ¨ User-selectable design Fragment schematic viewing | a | ||
| ¨ User-selectable Object search and schematic viewing | a | ||
| 5. Comprehensive RTL Language Support | VHDL or | VHDL or | |
| VHDL and | |||
| 6. Create designs using a specific FPGA Vendor ¨ Create design using ALTERA ONLY ¨ Create designs using XILINX ONLY ¨ Create Designs LATTICE ONLY | (L1 Altera (L1 Xilinx (L1 Lattice Version) | (L3 Altera Version) (L3 Xilinx Version) | |
| 7. Create Designs using any FPGA vendor | with | with | |
| 8. ASIC Synthesis | with |