SystemVerilog Support
Precision Synthesis: The definitive leader
With the new design constructs available in the SystemVerilog IEEE-1800 standard, engineers can leverage the language’s new coding shortcuts, abstraction extensions, and constructs that help eliminate mismatches between simulation and post-synthesis results. By writing intuitive, more concise, and more verifiable code, designers can more easily implement complex models and reduce risk of hard-to-find coding errors.
Fortunately, the new extensions are easy to adopt and incrementally integrate into existing RTL. SystemVerilog should be thought of as an extension to the existing Verilog standard as opposed to a quantum leap in design methodology. Along with its assertion and testbench constructs, the language offers a unified design and verification environment to realize greater productivity across the entire design cycle.
Precision is the definitive leader in SystemVerilog for FPGA synthesis, featuring near-complete coverage of the language’s synthesizable sub-set. Among the constructs supported are user-defined types, enumerated types, structures, unions, interfaces, packages, and enhancements to tasks, functions, procedural blocks, case statements, and loop statements, and many others. Customers have already implemented SystemVerilog designs onto FPGAs using Precision Synthesis. For any questions about Precision SystemVerilog support, contact dcs_info@mentor.com.
Tech Pubs
SystemVerilog is not a completely new hardware description language (HDL). With its rich set of extensions to the existing Verilog HDL, SystemVerilog is fully backward compliant with Verilog. Many of these extensions to Verilog make it easier to create accurate, synthesizable models of designs of any size. These extensions also make SystemVerilog easier to use and are truly beneficial to every engineer currently working with Verilog. This paper dispels the myth that only system designers need SystemVerilog, describing various enhancements of interest to all Verilog (and even many VHDL) users, regardless of the size or type of designs being modeled. Request the Tech Pub
Software Evaluation & Multimedia Presentations
Precision RTL Plus offers an improved way of designing FPGAs and dramatically increases designer productivity by providing several industry-first capabilities that enable every designer, regardless of level of expertise, to reach timing closure faster, minimize the impact of late cycle design changes, and make efficient use of FPGA architectural blocks. Request your free evaluation software today.
Learn how SystemVerilog helps FPGA designers code at higher levels of abstraction and for better verification. Using a sample design, this brief demo presents the benefits of SystemVerilog's design features and Precion's extensive support of the various language constructs. View Today