Technical Publications

With the advent of advanced HDLs that provide new and powerful language constructs, such as SystemVerilog, hardware modeling styles can now be enhanced both in terms of abstraction levels and overall efficiency. Developing concise, accurate designs entails learning how SystemVerilog features can be effectively used to design efficient and synthesizable models for both ASICs and FPGAs.

This paper will focus on the impact of new extensions and constructs in SystemVerilog on hardware designs and describe the usefulness and compatibility of these constructs vis-à-vis pure Verilog constructs

SystemVerilog has experienced broad adoption in verification, but not until recently did it receive much attention for its design constructs. The common explanation for this is that verification is the primary bottleneck in the design schedule; hence verification enhancements should logically be of the greatest interest. Recent studies show, however, that RTL implementation consumes nearly half of the design cycle, meaning that coding methodologies are far from perfect. SystemVerilog design constructs are intended to address the inefficiencies of conventional RTL design. This paper focuses on the set of language's constructs that raise the level of design abstraction to make RTL coding more intuitive, readable, and maintainable.

As FPGAs continue to increase in capacity, functionality and performance, FPGA developers are not only faced with design challenges and issues in achieving timing closure, but they must also find ways to reduce the overall design cycle time. They must find efficient synthesis and simulation methods, as well as techniques and methodologies to reduce place-and¬route runtimes. But the bottom-line goal remains the same -- get the job done. Choosing a methodology that can allow designers to pick the best silicon for the task and provide reduced cycle times is key.

This paper covers a project that is using advanced functional verification methods to verify a RTCA DO-254/EUROCAE ED80 Level A/B design. These methods include Constrained Random Simulation, Design Intent Specification (designer-added assertions), the Total Coverage Model (Unified Coverage Database), and Formal Verification (formal model checking). The project is a real design currently being developed at Rockwell Collins.

Interest in DO-254 first occurred in Europe and has since spread to the US commercial aircraft industry. If you are being asked about your company's DO-254 direction and compliance, but have been overwhelmed with information on the subject, then this article is for you. This article presents DO-254 for the novice, boiling down the standard, reducing it to its essential points so that you will be ready to respond with confidence, as well as understand its potential impact on your products or services.

The flexibility offered by field-programmable gate arrays (FPGAs) has made design iterations an integral part of the design process. Traditionally, engineers quickly wrote hardware description language (HDL) for their design, ran synthesis and place-and-route, programmed the FPGA, and verified the design functionality directly in hardware. If a performance issue or a functional bug was discovered, appropriate modifications were made to the HDL, followed by a time-consuming resynthesis and re-place-and-route to obtain a new FPGA bitstream and re-testing in hardware. The resulting long runtimes make this traditional approach impractical. This article will explore an inremental design approach that provides run-time savings and preserves quality-of-results.