FPGA/PLD Technical Publications Listing

In-field logic updates provide unprecedented flexibility. The Lattice TransFR solution uniquely allows designers to update logic without disturbing system operation. The solution combines the inherent flexibility of the LatticeXP FPGA's dual SRAM + FLASH configuration spaces with easy-to-use, no-cost ispVM software.

This paper presents a hardware platform that makes use of dynamic reconfiguration to increase computational potential of a simple microcontroller. Two sample applications demonstrate the transparency of this approach in terms of application programming.

With today's ever-increasing bit rates, faster edge rates, higher clock speeds, and technology that is driving voltages down and compressing the physical size of systems, signal integrity is a key issue in system design. This article examines at SI in areas such as package crosstalk, signal termination, power plane integrity, and signal alignment for jitter compensation. SI at the board level, including simulation, is also covered.

Embedded processor-based Platform FPGAs have placed new demands on tool providers. With hardware and software flows converging on the same device, users are looking to retain their productivity through simplified, intuitive and interoperable tool environments. The current generation of Xilinx Platform FPGAs with powerful RISC processors and multimillion-gate capacities requires powerful and matching co-verification methodologies. With the availability of Mentor Graphics? Seamless CVE, you now have access to an ASIC-strength, best-in-class debug solution. This article introduces the concept of co-verification, and describes its role, relevance, and realizable benefits in the context of programmable systems. The paper also explains the development work done in cooperation with Mentor Graphics to extend existing IBM PPC405 HW/SW co-verification solutions to more effectively target Xilinx devices.

In a typical FPGA design flow, a designer begins with writing the RTL code, performing functional simulation, running synthesis and place and route, and then further verifying the implementation with timing analysis and hardware debug. These operations can be executed in a graphical user interface (GUI) environment or "behind the scenes" by using scripts. Most EDA software tools, including those from Mentor Graphics and Altera, offer command-line (or shell) and industry-standard tool command language (Tcl) scripting support. By using command-line and Tcl scripting, designers can enhance their design flows and improve productivity.

This application note describes a dynamic phase alignment (DPA) application for networking interfaces in a Virtex-4™ device. The reference design performs bit alignment, word alignment, and real-time window monitoring.

As Altera FPGAs have evolved to become closer in application space to ASICs, FPGA design flows have become fundamentally similar to ASIC design flows. Together, Altera and Mentor Graphics have collaborated to provide innovative technologies to speed system design and take advantage of the programmable nature of FPGA devices for in-system verification. This technical paper provides an overview for ASIC designers moving to FPGA design.

Till recently, FPGA and CPLD design tools could automatically optimize designs for performance and area utilization, but would still leave power management largely up to the designer. In 2005, push-button PowerPlay power optimization technology will be included in Quartus II software releases, which promises to l help optimize power consumption in addition to speed and area constraints in FPGA, CPLD, and structured ASIC designs.

One advantage of FPGAs over ASICs is the flexibility to make design changes in case of a modified specification or design error. Traditionally, customers missed this advantage as they moved from FPGAs to standard-cell or structured ASICs. This paper presents two flexibility features that allow you to enjoy added FPGA benefits when you go to volume production, at prices below structured ASICs.

The next-generation challenge faced by mainstream FPGA EDA tool vendors is to leverage point tool expertise and thus meld apparently contradictory trends - higher levels of abstraction on the one hand and greater dependence on specific physical characteristics on the other - into a coherent design methodology and highly productive flow.

This paper highlights how and why a seamless migration methodology from FPGA to structured ASIC not only effectively addresses low to medium production volumes, but also provides designers a clear path for prototyping and program managers the flexibility to choose the most appropriate production option.

Non-volatile, reprogrammable LatticeXP FPGAs represent the 'affordable ideal' for many system designers, particularly those concerned with rapid logic availability, real time programming, security, board area and part counts.

The evolution of the programmable logic industry has fundamentally changed the value proposition of FPGAs to include high-volume, low-cost applications. A few years ago, the closest an FPGA could get to low-cost applications was as an ASIC prototyping tool. With the increasing development and production cost of ASICs, FPGAs today are becoming the de facto standard for system design in consumer, industrial, data communications, telecommunications, wireless, medical, and automotive markets. This paper from Altera describes the low-risk, low-cost, and fast-to-market advantages of the Cyclone II device family.

Reusing internal designs and incorporating commercial IP can help you quickly complete designs. However, some of this efficiency is lost if you are spending your design time unraveling this IP in order to discover its completeness and accuracy. This paper discuses a methodology to quickly complete the IP discovery process, enhanced through the use of FPGA Advantage?.

DSPs are found throughout the world of electronic equipment, from cell phones to flat-screen TVs. Dedicated DSP processors and cores are still a widely popular means of achieving digital signal processing needs. But as CPUs have incorporated arithmetic coprocessors and extensions that optimize digital signal processing tasks, and as other silicon alternatives have emerged, the necessity of a separate DSP device is no longer viewed as inevitable. In fact, there is increasing evidence that the negatives of discrete DSP devices outweigh their benefits. This paper discusses the emergence of FPGAs in DSP applications.

As today's FPGA designs get larger and more complex, a team design environment is essential. The management of design iterations is required so that several versions of the design are accessible at anytime in the future.

This paper discusses a version management system that provides file versioning, file locking, and version retrieval facilities. This enables all members of the design team to share the same database, with each individual working on different parts of the design. The whole system can then be built, based on different versions of each part, and can be verified in downstream operations such as simulation and synthesis.

Today's FPGA designs are becoming larger and more complex, with hundreds of macros, Intellectual Properties, and reusable parts of legacy designs. FPGA designers now face the huge challenge of rapidly describing the interfaces, i.e. hierarchies and interconnections, for a new design using these parts. However, traditional approaches spend too much time drawing large block diagrams or writing thousands of lines of structural HDL.

This paper describes how the spreadsheet approach of Interface-Based Design™ in FPGA Advantage? can enable design engineers to construct their FPGA design from the various sources for blocks (unique HDL code, IP cores, legacy HDL code, FPGA Vendor cores, etc) rapidly and efficiently, while also preparing for design documentation.

Part 2 of our DSP/FPGA series explores the design methodology and tools involved inimplementing high-performance DSP algorithms in FPGA

Step off the design iteration treadmill by using physical synthesis to rapidly solve timing problems in today's complex FPGAs. This article explains how physical synthesis technology works to concurrently optimize both logical and physical aspects of a design for single-pass timing closure.

As FPGA packages pass 1000 pins, managing the interface between the FPGA and board becomes a daunting task. This article discusses sharing the interface definition between the board and FPGA design worlds.

Read about the complete suite of vendor-independent design tools required for FPGA designers using today's new complex devices.

Now that your FPGA has a processor, it's time to think about an RTOS. This paper describes issues and considerations in choosing the best RTOS for your FPGA.

FPGAs have proven to be a valuable technology in today's electronic industry, offering performance, time-to-market, and cost advantages. Evidence of their pervasiveness is the fact that almost every Printed Circuit Board (PCB) now contains at least one FPGA. But, does the process of putting the FPGA on a PCB compromise those highly valued benefits? This paper examines the move from ASIC to FPGA technology, and the impact of FPGA on board integration today.

Critical-path delay can often be substantially reduced by re-timing, where combinational logic is moved through register boundaries.

Altera HardCopy Stratix Devices Offer an Alternative to ASICs - This paper discusses how HardCopy Stratix devices are an optimal solution for mid- to high-volume, low-cost, high-performance and low-power applications. It also discusses the unified design flow offered by Precision RTL Synthesis and Quartus II to target these devices.

As FPGA technology increases gate counts with each new generation, larger scale systems can be implemented using "Platform FPGAs" rather than ASICs. FPGA design starts have grown along with the technology's capabilities, exceeding those for ASIC by as much as 10 to 1 in 2002. To address the challenges these large FPGA-centric systems present, System-on-Chip (SoC) methodologies developed for ASIC-scale design, such as hardware/software co-verification, must be re-examined. In this article, we will demonstrate the application of the Mentor Graphics Seamless technology on a design targeting the Xilinx Virtex II Pro, with its embedded IBM PowerPC 405 CPU. This design will boot up the Nucleus Plus Real-Time Operating System (RTOS). We will also illustrate performance improvements over conventional HDL simulation when using Seamless.

Understanding device types and design flows is key to getting the most out of FPGAs. This article examines Do's and Don'ts for the FPGA designer, compares FPGA architectures, and considers the overall FPGA design flow. It also looks at the advantages and disadvantages of various FPGA technologies as well as the different types of FPGA usage.

The importance of considering the larger FPGA flow, in which the device is attached to a printed circuit board in a system, is also mentioned briefly. This larger, integrated flow becomes more critical as FPGA vendors continue to introduce more complex and powerful devices and as developers retarget designs to different technologies from different vendors.

With today's high-speed, high gate-count, high pin-count FPGAs the only constant in FPGA design is the changes that occur along the way, both at the interconnect level--to meet timing and loss requirements--and at the pin assignment stage within the FPGA itself. The great benefit of design flexibility offered by the FPGA is also one of the biggest nightmares for board designers. Companies would be wise to examine existing processes closely, ensuring that the significant flexibility and power offered by today's FPGAs doesn't becoming a doorway for potentially significant PCB implementation problems. Tools such as I/O Designer not only automate the schematic connectivity required for PCB layout and verification, but also document which signal connections are made to which device pins and indicate how these pins map to the original board-level bus structures. With the right software tools and close collaboration between the parallel paths of FPGA and PCB design, weeks can be trimmed from FPGA design and PCB implementation schedules, providing significant overall cost savings in the long term.

Being able to disable a clock benefits a design by lowering the dynamic power consumption significantly. QuickLogic?s dynamic clock disable feature can be easily integrated into new or existing designs by adding an enable signal to incoming clocks. Transitions from clock enable to disable, and back, are done safely and without glitches. When used with an efficient power management scheme, devices consume the lowest power possible and keep applications running significantly longer than before.

This paper discusses how FPGA designers can generate optimal HDL code for DSP functions to obtain optimized system performance. An implementation example using Altera Stratix II devices and Mentor Graphics tools is described.

This paper explores the integration of hard disk drive (HDD) technology into embedded applications, with a focus on consumer electronics. The main points of interest in this instance are:

• Performance
• Power
• Common interfacing requirements for some of the current HDD products
• Different system architecture implementations for connecting mini-disk drives to some of today’s prevalent low power embedded microprocessors
• Trade-offs that need to be considered for a given application

This paper describes techniques to automatically capture designers' intent and achieve optimal solutions for DSP-based FPGA architectures. The proposed techniques support DSP applications by optimally mapping all the basic building blocks, such as multiply-accumulate, multiply-add, multipliers and adders. Various applications, including fully parallel FIR filters, are illustrated.

Transceivers have become commonplace in many applications across all markets. This drive, fuelled by the desire to move more data, is supplemented by the emergence of many new transmission protocols. Today’s FPGAs with embedded transceivers support many widely accepted serial protocol standards, including Gigabit Ethernet, PCI Express, XAUI and Serial Rapid IO. Maintaining signal integrity is a key element for the successful implementation of these standards within high bandwidth applications. This paper discusses the complex issues facing system designers, and FPGA-based solutions that support high-speed applications and protocols.

This article compares and contrasts FPGA alternatives with regards to their power-up capabilities. The paper presents a typical implementation of a system with NVM FPGA and SRAM FPGA, and also highlights a highly effective solution for engineers specifically concerned about design time and cost.

With their shorter development times, FPGAs and structured ASICs are a viable solution for shrinking market windows. This paper discusses a case study in which Infineon Technologies sought alternative solutions and elected to design with Altera Stratix FPGAs and HardCopy structured ASICs. It also discusses how Mentor Graphics EDA software can accelerate overall system design.

The variable-input look-up table (LUT) architecture has been a fundamental component of the Xilinx VirtexTM architecture first introduced in 1998. This unique architecture enables flexible implementation of any function with eight variable inputs, as well as implementation of more complex functions.

The faster the frequency and the smaller the FPGA, means the increased risk for interference and compromised signal integrity. Read more about Xilinx and Mentor Graphics' partnership to ensure signal integrity from design to board.

With the increasing density and complexity of field programmable gate arrays (FPGAs), programmable architectures are becoming more attractive for implementing embedded system designs. FPGA manufacturers are continually adding hard intellectual property (IP), including increased memory, I/O standard support, and digital signal processing (DSP) functionality, which increases system performance and minimizes the need for peripheral devices.

The Spartan^TM-3 FPGA logic resources include not only the four-input look-up tables that have become the standard building block of FPGAs, but also dedicated resources that provide fast and efficient implementation of special functions. These resources are automatically selected and optimized by Mentor Graphics synthesis tools and Xilinx implementation tools. However, the user should consider creative ways of applying these resources when the design is created.

In order to minimize design-to-production timescales, it is important that potential downstream problems be identified as early in the design process as possible. Through the use of a comprehensive HDL development environment with built-in checking functionality, you can find and isolate several classes of design errors and dramatically reduce the cycle times needed to successfully complete complex FPGA and ASIC designs.

This paper looks at reuse from a completely different perspective: Is there a methodology to help you reuse existing HDL code that was not initially designed for reuse? This is practical reuse - a working methodology for getting your next design quickly completed, by reusing code that already exists at your corporation.

Finite state machines are widely used in digital circuit designs. Generally, when designing a state machine using an HDL, the synthesis tools will optimize away all states that cannot be reached and generate a highly optimized circuit. Occasionally the optimization is not acceptable. For example, if the circuit powers up in an invalid state, or the circuit is in an extreme working environment and a deficiency sends it into an undesired state, the circuit may never resume its normal operating condition.

This paper discuses a general methodology when creating a state machine using the HDL Designer SeriesTM State Diagram Editor. You can specify the design so that synthesis tools will not optimize away those unused states, thus a "safe" state machine can be generated.

Are you spending time creating and updating design documentation by hand? HDL Designer Series can significantly reduce the time it takes to accurately create documents in order to communicate with your internal and external customers. This paper provides an overview of the approach to solving these issues:

• You just inherited a large, existing design and you need to quickly understand and document it
  
• You need to share a design with others via the web
  
• You need to publish design documents

With FPGA designs and teams growing, one of the biggest challenges is sharing design data, decisions, and intent. This paper describes using HTML in conjunction with your design environment to share design info inside and outside your design team.

FPGAs provide an excellent platform for rapid development of applications in the fast-moving wireless LAN arena. This paper discusses SOHO applications of Xilinx Spartan series FPGAs.

Interest in DO-254 first occurred in Europe and has since spread to the US commercial aircraft industry. If you are being asked about your company's DO-254 direction and compliance, but have been overwhelmed with information on the subject, then this article is for you. This article presents DO-254 for the novice, boiling down the standard, reducing it to its essential points so that you will be ready to respond with confidence, as well as understand its potential impact on your products or services.

SystemVerilog is not a completely new hardware description language (HDL). With its rich set of extensions to the existing Verilog HDL, SystemVerilog is fully backward compliant with Verilog. Many of these extensions to Verilog make it easier to create accurate, synthesizable models of designs of any size. These extensions also make SystemVerilog easier to use and are truly beneficial to every engineer currently working with Verilog. This paper dispels the myth that only system designers need SystemVerilog, describing various enhancements of interest to all Verilog (and even many VHDL) users, regardless of the size or type of designs being modeled.

Today millions of users depend on spreadsheets, the most popular being Microsoft Excel, to organize, manage, analyze, model and generate numerical and text data. Spreadsheets are now making their way into hardware design. This paper covers the details of using the Interface Based Design (IBD) editor provided by Mentor Graphics HDL Designer Series(tm) to develop spreadsheets for hardware design.

Have you ever wondered about the quality of code you are writing or that you plan to reuse from another engineer? Many teams have codified their RTL coding experiences into style guides providing rules and guidelines for creating designs. Unfortunately, these guides are rarely used or remembered. What if you could set up a tool that reflected your style guide? What if that tool could automatically provide you with a score representing the quality of your code? This paper presents how you can set up code quality assessment via rules and the scoring mechanism so your whole team can develop quality, re-usable code during your next project.

When the decision is made to convert RTL code from one language to another, mistakes are unacceptable — the functionality of the new code must match that of the old. Any differences can lead to expensive and time consuming re-spins of the device. Unfortunately, mistakes are easy to introduce but difficult to find. This paper describes a methodology for automatically detecting all of the differences when converted RTL.

Many of today's large, complex designs contain thousands of lines of Verilog or VHDL code, developed by teams of engineers, often located at multiple locations worldwide. As a simple mistake in just one line of code can cause a schedule delay while the issues is debugged, it is crucial that code is checked against coding standards and best practices during development. In addition, it is important for the team to follow a common methodology for checking all source code to ensure that errors are caught early in the design process.

FPGAs are an excellent fit for video and image processing applications, such as broadcast infrastructure, medical imaging, HD videoconferencing, video surveillance, and military imaging. This paper discusses the trends in video and image processing, as well has how FPGAs solutions from Altera, when combined with Mentor Graphics design and verification tool suite, can improve cost, performance, and productivity for many video and imaging applications.

Ever since hardware description languages (HDLs) were first put into use to specify electronic designs, designers have recycled code. You gain new insights into the use of these HDL descriptions by copying and modifying - with the requisite permissions of course - existing examples. In most cases, code that is recycled probably was never originally meant to be used "as-is". The key to recycling is to quickly figure out how much work is required in order to decide whether or not recycling is practical. In his paper, Tom Dewey analyzes if reusing RTL code is practical and how to accomplish it using HDL Designer.

This application note explains how to work with the ClearCase tool from within HDL Designer™. It covers two main issues: How to set up your library mapping in HDL Designer, and how to revert to older versions of your design.

This application note highlights the requirements of a productive and efficient team-based design environment, and outlines how you can benefit from a possible implementation of such an environment. It also shows you how to implement a highly productive team-based design environment using the HDL Designer Series of tools.

With the re-write of the Concurrent Versions System (CVS) interface in HDL Designer Series, there has been a change from the previous use model. This application note walks you through setting up Version Management (VM) in HDL Designer Series, targeting CVS as your VM interface, and using the new CVS interface.

HDL Designer Series provides version management support, including the revision control system (RCS) shareware environment. RCS provides a way to save multiple backups without using a lot of disk resources. This appnote provides an overview of the RCS environment within HDS, including file management.

With today's ever-increasing bit rates, faster edge rates, higher clock speeds, and technology that is driving voltages down and compressing the physical size of systems, signal integrity is a key issue in system design. This article examines at SI in areas such as package crosstalk, signal termination, power plane integrity, and signal alignment for jitter compensation. SI at the board level, including simulation, is also covered.

Designing high-speed memory interfaces is a challenging task. Xilinx has invested time and
effort to make it simple to design such interfaces using the Virtex-IIT and Virtex-II ProT FPGAs. This application note discusses the challenges presented by this task together with various techniques that can be used to overcome them, while illustrating the key concepts in implementing any memory interface. All examples used in this application note assume a DDR-1 interface on an XC2VP20FF1152-6 Virtex-II Pro FPGA. The interface speed is 200 MHz.

With the ASIC approach becoming more challenging and FPGA cost effectiveness improving, utilizing FPGAs is becoming more attractive for high-volume designs. An acceleration of this trend requires that FPGAs be precisely targeted to the requirements of high-volume designers.

This white paper examines specific factors impacting the optimization of an FPGA architecture in terms of the logic block, I/O support, external memory interfacing and configuration memory support. The paper concludes with an overview of the Lattice ECP/EC architecture.

Over 40% of FPGA design projects fall behind schedule. In order to reduce the risk of delay in product delivery, changes need to be made not just in verification but also in the design process itself. Design simplification must be a principle that starts at the beginning of the project life cycle – before verification of complex code has become the bottleneck that delays project delivery. This paper examines two concepts here that can simplify the implementation of a complex FPGA design: the use of SystemVerilog and vendor-independent modeling.

The Quartus II design software version 5.0 introduces new incremental compilation technology that, when combined with Mentor Graphics Precision Synthesis software, delivers a high performance, highly productive environment for high-density FPGA designs.

With a new integrated design flow from Mentor Graphics, you can use I/O Designer to adjust pin assignments to benefit your FPGA placement, and invoke Precision Synthesis to physically optimize your design based on the new pin assignments.

Advanced DSP-48 inference capabilities in Precision Synthesis, combined with the innovative DSP-48 slice in Virtex-4, provides a powerful DSP system solution if you're considering designing with today's advanced FPGA architectures.

There are many ways to manage a project using source control, each with its own uses and benefits. This paper covers topics that help produce a system that is both effective and usable for any given situation, including considerations such as: How will the project be used once it is checked out? How are the input files organized? How will the constraints be managed? How can scripting help? And of course, which files and directories need to be under source control?

This paper outlines Dillon Engineering, Inc.'s guidelines for success in implementing complete radar processing algorithms on a single multi-million gate FPGA. Most of these systems involve FFT processing along with other DSP algorithms. Dillon has recently implemented several radar processing systems on single FPGAs, and attributes this success in large part is due to its ability to reuse IP as well as the reliability of the tools available in its design flow.

In order to keep your HDL code technology independent, a good synthesis tool must offer an automatic inferring (recognizing) capability. In addition to enabling FPGA designers to freely target a different technology, Precision? Synthesis also provides optimal quality of results (QoR) based on heuristic algorithms. In terms of writing RTL behavior for RAM storage hardware, this paper shows how you can either specifically instantiate certain technology cells or let Precision Synthesis automatically infer RAMs from your intent HDL source code.

FPGAs are increasingly being used for mission-critical applications in hazardous operating environments (space, military, medical etc.). In these applications the circuit must be fault-tolerant, especially finite state machines (FSMs), where failures are very hard to detect. Most single-fault-tolerant FSMs are implemented using triple module redundancy (TMR) or by using a single-error-correcting (SEC) code during state encoding. Typical instances of SEC employ a minimal encoding (binary, Gray etc.) scheme to force a Hamming distance of three. Commercially available FPGA synthesis tools only implement error recovery to a specified recovery state. They do not implement error correction. In this paper, we investigate a general technique of adding Hamming error checking bits to any encoding style of FSMs to automatically recover from single event upsets (SEUs) within the same clock cycle. We shall report on the efficacy of this method to correct single-bit errors and detect two-bit errors. Area and delay results of using this technique on selected designs are also explored.

When you come across designs where constraints are available in the UCF format, you may need to convert them into the industry-standard SDC timing constraint format. Precision? Synthesis provides a method to convert timing constraints, but there are some considerations that you must take into account when using this translator. This application note details these considerations and provides clear instructions on how to use this flow when required (or whether to use it at all).

By supporting new features like DLL (in the Virtex, Virtex-E, Spartan-II), and DCM (in the Virtex-II and Virtex-II Pro), Precision RTL allows you to seamlessly integrate these critical Xilinx components into your designs. Automatic clock propagation across DCM/DLL, combined with an integrated place and route environment makes Precision RTL a powerful synthesis solution for designing with newer Xilinx devices. In addition, Precision RTL provides excellent DCM/DLL timing analysis and attribute-editing capabilities during post-compile or post-synthesis. This application note provides DCM/DLL design & coding guidelines, along with code snippet examples that show you how to instantiate DCM and pass its attributes in VHDL and defparams in Verilog. The paper also provides further links from where you can download a complete set of CLKDLL and DCM coding examples for both VHDL & Verilog.

This application note describes how to generate the Xilinx MicroBlaze 32-bit soft processor core netlist from the Embedded Development Kit (EDK), and how to seamlessly integrate it into Mentor Graphics? Precision? Synthesis flow. Designers can thus bring the netlist into the Precision Synthesis design environment as part of a team-based design with minimal user intervention.

ROM decoding can create multiple levels of logic in an FPGA design. Not only could this result in critical timing paths and other problems, but your runtimes may also suffer. It is essential for a synthesis tool to take advantage of rich FPGA RAM architectures. This application note shows how smart ROM inferencing, combined with advanced ROM to Block RAM mapping algorithms, provides a powerful synthesis solution for designing with today's advanced FPGA memory hardware architectures.

The Precision? Physical Synthesis product offers a suite of tools that allows users to create optimum FPGA designs. The PreciseView tool helps you to manually modify the layout to achieve timing closure. It ensures that edits produce legal results and provides immediate timing feedback. Even so, a great deal of effort may be required in high-end designs. What happens if a small change (more common in larger, complex designs) is required? Starting over is simply not acceptable. This paper describes a placement reuse design flow to address those inevitable last-minute engineering change orders (ECOs) with minimal disruption to your product schedules. The combination of advanced deterministic naming algorithms with smart placement overlay commands provides a comprehensive placement reuse flow to manage ECOs. This flow is vital to creating a practical and predictable design environment, and should be well understood by the end user.

Control-path and board-management functions are increasing in complexity, and traditional CPLD architectures cannot cost-effectively support the increased functionality required. Leveraging Altera?s new low-cost MAX II CPLD family with its instant-on, non-volatile product attributes and unique features can help designers introduce, new, smaller and more powerful systems at a lower cost. These benefits can be achieved using the same easy-to-use tools as previous CPLD generations, reducing time to market and accelerating the learning curve.

As hardware and software flows converge on the same embedded processor-based platform FPGAs, users are looking to retain their productivity through simplified, intuitive and interoperable tool environments. Xilinx Platform Studio (XPS) is a system-design IDE that supports open interfaces, making tool integration easy and painless. Embedded processor designs using Xilinx IP require XPS for platform assembly, configuration and implementation. However, many users also often use Precision? Synthesis or LeonardoSpectrum? products to implement their custom IP blocks. This article outlines scenarios that allow users to easily integrate blocks implemented using Mentor Graphics? design tools with the rest of the processor design.

Altera's next-generation Stratix II family introduces a revolutionary logic structure for efficient implementation of complex data processing and arithmetic functions. This paper discusses how Precision Synthesis uses it's extensive knowledge of Stratix II architecture for optimal implementation of your designs.

This paper will provide you with background information on a technique used by FPGA vendors to enable design reuse. Following this background information we will demonstrate how the Mentor Graphics Precision Physical tool makes design reuse straightforward and easy for the typical FPGA designer.

As FPGA capacities exceed millions of gates, a problem surfaces that looks very familiar to ASIC designers. The physical effects of routing and interconnect become the dominant factors in the final performance of the chip, while device delays become largely irrelevant. A word of warning, however, to engineers proficient in the techniques used to negate the problems faced in the ASIC space. Be aware that while the problems may look similar, the solutions and tools used to solve the same issues in the FPGA space are quite different. While the key consideration is still: "it's not what the device is, but where it is", there are other factors of importance, as this paper will explain. Trying to achieve FPGA timing closure in the traditional way, without the correct application of physical synthesis techniques, not only results in less than optimal performance but will also end up as a painful and unpredictably long process involving many place-and-route iterations. This paper outlines some real-world case studies explaining how to correctly apply physical synthesis using, as examples, the technologies driving Mentor Graphics' Precision family of products.

Most HDL-based designs use either a top-down or bottom-up (block-based) design methodology. Depending on size, type, design complexity, design environment or existing flows, one may be more suitable than the other. Each of them shares the same synthesis functions, algorithms, and flows. It is imperative that you choose the right design methodology for your designs. Both methodologies have their own advantages and disadvantages in terms of providing the quality of results (QoR), runtime, timing, and area utilization. In addition to these two design methodologies, it is also important to understand some fundamentals of how to apply the design constraints. This paper outlines the criteria you need to consider for selecting the appropriate design methodology.

The evolution of the programmable logic industry has fundamentally changed the value proposition of FPGAs to include high-volume, low-cost applications. A few years ago, the closest an FPGA could get to low-cost applications was as an ASIC prototyping tool. With the increasing development and production cost of ASICs, FPGAs today are becoming the de facto standard for system design in consumer, industrial, data communications, telecommunications, wireless, medical, and automotive markets. This paper from Altera describes the low-risk, low-cost, and fast-to-market advantages of the Cyclone II device family.

A major transformation is occurring in the area of electronic system design. Programmable logic devices are providing designers with an environment to develop circuits with densities of 10M+ system gates, frequencies over 300 MHz, and embedded processors, enabling complete system integration. This technology leap is causing a shift in the design process by providing a comprehensive methodology outside the ASIC arena.

The PCI core is one of Xilinx most popular off-the-shelf IP solutions. Learn how to quickly and easily incorporate this popular core into your next FPGA design.

The Verilog 2001 standard approved in June 2000 by IEEE includes several practical and useful extensions to the language. Learn about the new verilog 2001 constructs as they apply to FPGA synthesis.

As the use of FPGAs continues to become the hardware design engineer's choice for implementing custom logic and Intellectual Property (IP), there is anever-growing need for the EDA industry to standardize on a common constraint language. This standardization will ensure interoperability between FPGA synthesis and"place-and-route tools, and will allow accurate description of vdesigner intent" to achieve design closure. This paper explains how the use of a common constraint language (SDC) to set up constraints will expedite your next FPGA design.

As more dedicated functional blocks are embedded into FPGAs architecture, the challenge to a synthesis tool to accurately handle the functionality and timing across these blocks increases. This paper highlights Precision RTL's capability to be able to propagate clock values across a FPGA's PLL (Phase Locked Loop) block. As opposed to the traditional approach of treating a PLL block as a black-box, Precision RTL can extract the primary input clock and also calculate the values of the output clocks of the PLL. This enhanced capability translates to lesser dependency on user intervention (to setup clocks) and to a better timing estimation by the synthesis tool.

Some of the latest-generation FPGAs have specialized architectures that can lead to blazing fast implementations of DSP algorithms. This paper examines applications such as FIR filters, and explains RTL coding techniques for taking advantage of multiply-accumulates as well as the high-speed memory structures in Altera's new Stratix family.

Simply using a Rad-hard technology is not sufficient to provide low susceptibility to high-radiation environments. This article discusses design techniques such as TMR and TMR-CC and how to apply them in FPGA synthesis.

Learn how to apply physical synthesis techniques to reduce your silicon cost by as much as 30% by saving a speed grade on your next design.

Whenever hardware designers have to put multiple internal and off-the-shelf IPs together in a prototyping solution, the verification of this set-up becomes a real challenge. Using an H.264 decoder application, this article discusses what difficulties the verification engineer has, and how the problems of verifying a complex design consisting of many IPs can be overcome.

Managing timing constraints often seems like the painful but necessary evil of FPGA design. But "proper constraints are part of proper FPGA design," and adhering to a constraint methodology is important for implementing a design correctly. With more complex clocking schemes in today's FPGAs and the prevalence of high-speed I/O interfaces, constraint management is even more critical to system design. Without proper timing constraints, violations are not seen and the timing analysis is incomplete, potentially leading to faulty in-circuit operation that is difficult to debug.

This article looks at how high-end FPGA I/O cells interface to DDR3 SDRAM to take advantage of these speed and power benefits. It examines how leveling is achieved in the FPGA for operation with a DDR3 SDRAM DIMM memory, the benefits of using dynamic on-chip termination (OCT) to match the impedance on a bidirectional bus and save power, and the advantages of using variable I/O delay for deskew within a DQS group. It also discusses the importance of simulating with tools such as Mentor Graphics HyperLynx to ensure the best eye quality.

The flexibility offered by field-programmable gate arrays (FPGAs) has made design iterations an integral part of the design process. Traditionally, engineers quickly wrote hardware description language (HDL) for their design, ran synthesis and place-and-route, programmed the FPGA, and verified the design functionality directly in hardware. If a performance issue or a functional bug was discovered, appropriate modifications were made to the HDL, followed by a time-consuming resynthesis and re-place-and-route to obtain a new FPGA bitstream and re-testing in hardware. The resulting long runtimes make this traditional approach impractical. This article will explore an inremental design approach that provides run-time savings and preserves quality-of-results.

As FPGAs continue to increase in capacity, functionality and performance, FPGA developers are not only faced with design challenges and issues in achieving timing closure, but they must also find ways to reduce the overall design cycle time. They must find efficient synthesis and simulation methods, as well as techniques and methodologies to reduce place-and¬route runtimes. But the bottom-line goal remains the same -- get the job done. Choosing a methodology that can allow designers to pick the best silicon for the task and provide reduced cycle times is key.

SystemVerilog has experienced broad adoption in verification, but not until recently did it receive much attention for its design constructs. The common explanation for this is that verification is the primary bottleneck in the design schedule; hence verification enhancements should logically be of the greatest interest. Recent studies show, however, that RTL implementation consumes nearly half of the design cycle, meaning that coding methodologies are far from perfect. SystemVerilog design constructs are intended to address the inefficiencies of conventional RTL design. This paper focuses on the set of language's constructs that raise the level of design abstraction to make RTL coding more intuitive, readable, and maintainable.

FPGAs have become the multi-purpose tools of hardware design. No other off-the-shelf semiconductor device is capable of solving so many application problems. The versatile logic cell architecture of the typical FPGA allows it to be used for everything from an MP3 player to a guided missile. However, as FPGA architectures have evolved to address a wider range of applications, they have also become more complicated to use. Today's design engineer needs help to efficiently map his design to today;s FPGAs.

Next-generation interconnects continue to press the limits of both hardware and software technologies. The need for increased quality of service (QoS), channel separation, fairness and data integrity are just a few requirements that deserve mention. PCI Express is one such interconnect that is finding its way into a growing variety of application spaces.

While FPGA manufacturers' tool suites offer a quick and effective way to target an existing starter board, the flow does not necessarily provide the most optimal integration into the designer's chosen CAD flow. A designer wanting to take advantage of the MicroBlaze embedded processor IP while trying to minimize deviations from their chosen CAD flow might consider a strategy that uses Platform Studio primarily as a netlist generator for their custom application, but then uses their preferred synthesis and debug tools for the remainder of the design. By following some straight-forward guidelines, Precision Synthesis can successfully be used to synthesize MicroBlaze subsystems.

With enormous design sizes and with many engineers working on different parts of the same design, it is essential that a synthesis tool provide flexibility to compile different design blocks separately. A “bottom-up flow” where each designer can synthesize his or her design block as a separate design and then incorporate it into the top level design for complete design synthesis is an effective solution.

FPGA vendors gain a unique perspective on the overall telecom/datacom market space because programmable logic devices have found their way into a broad swath of products, ranging from mass-produced set top boxes to next generation core routers. At the same time, working closely with individual equipment vendors to implement programmable solutions provides insights into the challenges confronting infrastructure providers and the strategies that they have developed in response.

The increase in size and complexity of many of today’s high-speed wireless and video algorithms has driven the need for a design methodology to provide designers with a rapid path from creating algorithms in C++ to RTL running in hardware. With their rapidly growing capacity and dedicated arithmetic hardware, platform FPGAs have become an attractive and cost-effective solution for addressing the massive parallelism required by these algorithms. This article will focus on the FPGA features of Catapult C, and how the close integration with Precision RTL maintains the amazing productivity gains of the algorithmic C++ synthesis design flow.

With the convergence of communications and computing technologies driving the adoption of PCI Express, Gigabit Ethernet and Serial RapidIO(tm) protocols into cost-sensitive markets, the time is right for applications such as bridging and endpoint applications to utilize low-cost FPGA with embedded transceivers. These applications are rapidly becoming commonplace, however designs can still be challenging, both at the board level and for the FPGA designer, where the technology is new.

As electronic systems grow larger and more complex, designers face new and increasing challenges in the design, verification, implementation and fabrication of those devices. This paper focuses on two of those challenges: the decreasing visibility of large integrated systems, be they in an ASIC or an FPGA, and the increasing number of bug escapes that result from a simulation-only verification flow. Those challenges can be solved by the combination of a design-for-debug (DfD) tool suite coupled to an optimizing compilation system that together provide a fast, efficient and flexible solution.

While many SERDES-based designs will continue to need a high performance FPGA fabric and I/O structure, there is a growing need for low cost solutions as well. PCI Express and Serial Ethernet based designs are replacing legacy PCI and Fast Ethernet interfaces. As these standards become ubiquitous and an integral part of FPGA designs, there will be a need for an accompanying low cost FPGA to handle the relatively lower performance bridging, co-processing and glue logic functionality of those designs.

Finite State Machines (FSMs) often serve as the critical control circuitry of any design. This article provides an overview of the factors that affect the performance and reliability of FSMs when synthesizing with Precision Synthesis.

Widely used in both automotive and consumer markets, microcontrollers provide a high level of system integration combined with a relatively low cost. However, there are hidden costs associated with these products.. Many microcontrollers equipped with specialized features and a fixed number of dedicated interfaces do not fulfill market requirements after a short evaluation period. Consequently, system suppliers are forced to redesign their hardware and software, in some cases even having to change the processor core.

Physically aware synthesis incorporates innovative physically aware optimization algorithms to further improve designs beyond the capabilities of traditional RTL FPGA synthesis tools. Moreover, users are free to use existing physical synthesis tools, such as Precision Physical or an FPGA vendor's physical synthesis options, in addition to physically aware synthesis if additional improvement is needed.