Technical Publications
Is SystemVerilog Only for System-Level Design
SystemVerilog is not a completely new hardware description language (HDL). With its rich set of extensions to the existing Verilog HDL, SystemVerilog is fully backward compliant with Verilog. Many of these extensions to Verilog make it easier to create accurate, synthesizable models of designs of any size. These extensions also make SystemVerilog easier to use and are truly beneficial to every engineer currently working with Verilog. This paper dispels the myth that only system designers need SystemVerilog, describing various enhancements of interest to all Verilog (and even many VHDL) users, regardless of the size or type of designs being modeled.
Achieving Quality and Traceability in FPGA/ASIC Flows for DO-254 Aviation Projects
With the recent FAA/EASA mandate, companies providing flight hardware for commercial aviation systems now must build their complex electronic hardware components (i.e., ASIC/FPGA) to the standard known as DO-254. Focusing on design assurance (including quality, traceability, and strict configuration management), the DO-254 standard can have a profound impact on a company's development processes and design flows.
This paper discusses the application of advanced methodologies and integrated tool flows for ASIC/FPGA design and verification, showing how to implement a high quality flow that provides the required assurance while maintaining cost and schedules.
Demystifying DO-254
Interest in DO-254 first occurred in Europe and has since spread to the US commercial aircraft industry. If you are being asked about your company's DO-254 direction and compliance, but have been overwhelmed with information on the subject, then this article is for you. This article presents DO-254 for the novice, boiling down the standard, reducing it to its essential points so that you will be ready to respond with confidence, as well as understand its potential impact on your products or services.
Integrating HDL Designer Series and FormalPro Tools
When the decision is made to convert RTL code from one language to another, mistakes are unacceptable — the functionality of the new code must match that of the old. Any differences can lead to expensive and time consuming re-spins of the device. Unfortunately, mistakes are easy to introduce but difficult to find. This paper describes a methodology for automatically detecting all of the differences when converted RTL.
Scoring with HDL Designer
Have you ever wondered about the quality of code you are writing or that you plan to reuse from another engineer? Many teams have codified their RTL coding experiences into style guides providing rules and guidelines for creating designs. Unfortunately, these guides are rarely used or remembered. What if you could set up a tool that reflected your style guide? What if that tool could automatically provide you with a score representing the quality of your code? This paper presents how you can set up code quality assessment via rules and the scoring mechanism so your whole team can develop quality, re-usable code during your next project.
RTL Analysis and Creation using Spreadsheets
Today millions of users depend on spreadsheets, the most popular being Microsoft Excel, to organize, manage, analyze, model and generate numerical and text data. Spreadsheets are now making their way into hardware design. This paper covers the details of using the Interface Based Design (IBD) editor provided by Mentor Graphics HDL Designer Series(tm) to develop spreadsheets for hardware design.
Is SystemVerilog Only for System-Level Design
SystemVerilog is not a completely new hardware description language (HDL). With its rich set of extensions to the existing Verilog HDL, SystemVerilog is fully backward compliant with Verilog. Many of these extensions to Verilog make it easier to create accurate, synthesizable models of designs of any size. These extensions also make SystemVerilog easier to use and are truly beneficial to every engineer currently working with Verilog. This paper dispels the myth that only system designers need SystemVerilog, describing various enhancements of interest to all Verilog (and even many VHDL) users, regardless of the size or type of designs being modeled.
Developing an Effective Methodology for Checking RTL
Many of today's large, complex designs contain thousands of lines of Verilog or VHDL code, developed by teams of engineers, often located at multiple locations worldwide. As a simple mistake in just one line of code can cause a schedule delay while the issues is debugged, it is crucial that code is checked against coding standards and best practices during development. In addition, it is important for the team to follow a common methodology for checking all source code to ensure that errors are caught early in the design process.
FPGA-Based Solutions for Video and Image Processing
FPGAs are an excellent fit for video and image processing applications, such as broadcast infrastructure, medical imaging, HD videoconferencing, video surveillance, and military imaging. This paper discusses the trends in video and image processing, as well has how FPGAs solutions from Altera, when combined with Mentor Graphics design and verification tool suite, can improve cost, performance, and productivity for many video and imaging applications.
Should You Reuse RTL?
Ever since hardware description languages (HDLs) were first put into use to specify electronic designs, designers have recycled code. You gain new insights into the use of these HDL descriptions by copying and modifying - with the requisite permissions of course - existing examples. In most cases, code that is recycled probably was never originally meant to be used "as-is". The key to recycling is to quickly figure out how much work is required in order to decide whether or not recycling is practical. In his paper, Tom Dewey analyzes if reusing RTL code is practical and how to accomplish it using HDL Designer.