Technical Publications
Incremental FPGA Synthesis
As FPGA devices have grown larger and more complex, the design process has become more challenging. Designers must now contend with a large number of complex embedded blocks in a single FPGA. This increase in functionality has led to long runtimes and difficulties in achieving timing closure. As a result, designers have turned to incremental design to alleviate this problem; however, the currently available solution requires designers to intelligently partition their designs early in the design process, limiting its acceptance in the market. A new capability providing all the desired benefits of incremental design without the manual up front work is highly sought by the FPGA designers.
Managing Timing Constraints with Precision Synthesis
Managing timing constraints often seems like the painful but necessary evil of FPGA design. But "proper constraints are part of proper FPGA design," and adhering to a constraint methodology is important for implementing a design correctly. With more complex clocking schemes in today's FPGAs and the prevalence of high-speed I/O interfaces, constraint management is even more critical to system design. Without proper timing constraints, violations are not seen and the timing analysis is incomplete, potentially leading to faulty in-circuit operation that is difficult to debug.
Raising the RTL Abstraction Level and Design Conciseness with SystemVerilog
With the advent of advanced HDLs that provide new and powerful language constructs, such as SystemVerilog, hardware modeling styles can now be enhanced both in terms of abstraction levels and overall efficiency. Developing concise, accurate designs entails learning how SystemVerilog features can be effectively used to design efficient and synthesizable models for both ASICs and FPGAs.
This paper will focus on the impact of new extensions and constructs in SystemVerilog on hardware designs and describe the usefulness and compatibility of these constructs vis-à-vis pure Verilog constructs
Implementing SystemVerilog for FPGA Design
SystemVerilog has experienced broad adoption in verification, but not until recently did it receive much attention for its design constructs. The common explanation for this is that verification is the primary bottleneck in the design schedule; hence verification enhancements should logically be of the greatest interest. Recent studies show, however, that RTL implementation consumes nearly half of the design cycle, meaning that coding methodologies are far from perfect. SystemVerilog design constructs are intended to address the inefficiencies of conventional RTL design. This paper focuses on the set of language's constructs that raise the level of design abstraction to make RTL coding more intuitive, readable, and maintainable.
The CHIPit UMRBus Communication System Opens New Ways of Design Verification
Whenever hardware designers have to put multiple internal and off-the-shelf IPs together in a prototyping solution, the verification of this set-up becomes a real challenge. Using an H.264 decoder application, this article discusses what difficulties the verification engineer has, and how the problems of verifying a complex design consisting of many IPs can be overcome.
Preserving Freedom of Choice When Designing FPGAs
As FPGAs continue to increase in capacity, functionality and performance, FPGA developers are not only faced with design challenges and issues in achieving timing closure, but they must also find ways to reduce the overall design cycle time. They must find efficient synthesis and simulation methods, as well as techniques and methodologies to reduce place-and¬route runtimes. But the bottom-line goal remains the same -- get the job done. Choosing a methodology that can allow designers to pick the best silicon for the task and provide reduced cycle times is key.
Real Incremental Design for FPGAs
The flexibility offered by field-programmable gate arrays (FPGAs) has made design iterations an integral part of the design process. Traditionally, engineers quickly wrote hardware description language (HDL) for their design, ran synthesis and place-and-route, programmed the FPGA, and verified the design functionality directly in hardware. If a performance issue or a functional bug was discovered, appropriate modifications were made to the HDL, followed by a time-consuming resynthesis and re-place-and-route to obtain a new FPGA bitstream and re-testing in hardware. The resulting long runtimes make this traditional approach impractical. This article will explore an inremental design approach that provides run-time savings and preserves quality-of-results.
Implementing DDR3 DIMMs With Modern FPGAs
This article looks at how high-end FPGA I/O cells interface to DDR3 SDRAM to take advantage of these speed and power benefits. It examines how leveling is achieved in the FPGA for operation with a DDR3 SDRAM DIMM memory, the benefits of using dynamic on-chip termination (OCT) to match the impedance on a bidirectional bus and save power, and the advantages of using variable I/O delay for deskew within a DQS group. It also discusses the importance of simulating with tools such as Mentor Graphics HyperLynx to ensure the best eye quality.
Managing Precious FPGA Resources
FPGAs have become the multi-purpose tools of hardware design. No other off-the-shelf semiconductor device is capable of solving so many application problems. The versatile logic cell architecture of the typical FPGA allows it to be used for everything from an MP3 player to a guided missile. However, as FPGA architectures have evolved to address a wider range of applications, they have also become more complicated to use. Today's design engineer needs help to efficiently map his design to today;s FPGAs.
Scatter/Gather DMAs for PCI Express-Enabled Embedded Systems
Next-generation interconnects continue to press the limits of both hardware and software technologies. The need for increased quality of service (QoS), channel separation, fairness and data integrity are just a few requirements that deserve mention. PCI Express is one such interconnect that is finding its way into a growing variety of application spaces.