Equivalence Checking for FPGA Design
Contributor: Jim Henson
Format: PDF Document
As both designs and the FPGAs used for these designs have grown into the millions of gates, FPGA designers are adopting more ASIC design processes, verifying the design with simulation at each step. But as the designs have grown larger, simulation runs have increased greatly. These large FPGA designs demand the verification tools used for ASIC design to minimize the time required for verification without compromising the coverage.