Scalable Verification
Mentor provides a complete set of advanced verification methodologies that:
- Improve productivity, predictability and quality
- Are based on standards (eliminate vendor lock-in and support any flow)
- Incorporate the best technology
- Span the entire SOC verification problem
OVM plus Questa in-depth
OVM for SystemVerilog
The Open Verification Methodology Enables Simulator, Verification IP, and Language Interoperability to Deliver on Promise of SystemVerilog.
OVM is based on the IEEE 1800 SystemVerilog standard and supports design and verification engineers developing advanced verification environments that offer higher levels of integration and portability of Verification IP. The methodology is non-vendor specific and represents interoperability with multiple languages and simulators. OVM is fully open, and includes a robust class library and source code
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The Questa™ advanced verification environment from Mentor Graphics® combines high performance and high capacity with the most advanced verification capabilities in the industry.
Assertion-based verification (ABV), testbench automation, and coverage-driven verification (CDV) are supported by a self-contained assertion engine, an advanced constraint solver, and extensive functional coverage features. This complete set of advanced verification methodologies are enabled by a flexible architecture that is unrivaled in the area of language support.
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of 2007
Technical Events:
- ADMS: Mixed Signal SoC Design Workshop (New)
Oct 16, 2008 - San Jose, CA
- EDA Tech Forum (Denver, CO)
Oct 14, 2008 - Denver, CO
- Accélérer et améliorer vos vérifications analogiques et digitales en partenariat avec Mentor Graphics
Oct 21, 2008 - Grenoble, FR
- Questa Verification Management Web Seminar
Oct 21, 2008 - online
Featured Scalable Verification Techpubs
Binding SystemVerilog to VHDL Components Using Questa
Binding SystemVerilog to VHDL Components Using Questa SystemVerilog offers a rich set of testbench automation capabilities, native assertions, and functional coverage. These features make SystemVerilog increasingly appealing to VHDL users who need to implement an efficient and effective functional verification methodology.
The Questa(tm) advanced verification environment offers native support of SystemVerilog, Verilog, and VHDL, making it easy to adopt SystemVerilog.
The flexibility provided by Questa's single kernel architecture enables VHDL users to easily attach SystemVerilog to existing VHDL components. The connection is made using the SystemVerilog bind function, which gives modules and program blocks access to both external ports and internal signals in the bound VHDL object. Among other things, you can use this capability to monitor VHDL functionality with SystemVerilog Assertions (SVA) or assess the functional coverage of VHDL designs.