Functional Verification

Conquer your growing verification challenges.

Vista, Questa and VeloceThe Mentor Graphics Functional Verification platforms-Vista, Questa and Veloce-deliver a high-productivity verification flow, optimized to your requirements. Tightly integrated to provide seamless transitions from ESL to emulation, transactions to transistors, with leading support for open, industry standards, these platforms help you conquer growing verification challenges, achieve schedule predictability and ensure rapid verification closure.

Processor-Driven Verification

White Paper: Current techniques of applying test vectors from an HDL testbench only begin to mimic processor bus behavior. The introduction of processor driven testbenches into the existing verification methodology... View White Paper

Verification Management Eases Those Re-spin Worries

White Paper: When verification is not under control, project schedules slip, quality is jeopardized and the risk of re-spins soars. These less-than-stellar outcomes seem to be happening more and more often. Firsttime... View White Paper

Learn More About Functional Verification

Verification Horizons Blog

Updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them. Hear from Dennis Brophy, Harry Foster, Tom Fitzpatrick and others. View All Posts

Verification Horizons Newsletter

Provides in-depth articles and practical knowledge about state-of-the-art functional verification techniques and technology. Verification Horizons

Transforming Verification On Demand Seminar Series

The complexity of SoCs is transforming functional verification, forcing the integration of multiple technologies into a flexible, open flow that integrates a broad arsenal of verification solutions. We have created a series of online technology seminars to help you transform your verification process.

Verification Management and Planning

Leveraging Questa Verification IP to Achieve More Verification with Less Effort

Improving Quality and Time-to-Market with Formal Verification

OVM/UVM

Learn from the contributing authors of the UVM/OVM Online Cookbook. This series of online seminars will show you how to create the pieces you need and integrate them to solve your particular verification problem. Watch and Learn

In The Press

Mentor Graphics Drives Broader Adoption of UVM

Mentor Graphics Drives Broader Adoption of UVM - Introducing UVM Express, a way to progressively adopt a UVM methodology and UVM Connect, which provides standard TLM 1.0 and TLM 2.0 connectivity between... View News Article

Industry Segments

Mentor Graphic's verification solutions are used across multiple industry segments and across all design and verification activities from design and testbench creation to design analysis, simulation, and management.

Semiconductor & IP

  • Processors, DSP
  • Graphics Chips/Cores
  • Interface Controllers
  • Switching Fabric
  • Comm. Controllers
  • Memory Systems
  • Audio/Video Codecs
  • Storage Processors

Networking/Data Communication

  • Local Area Networking
  • Optical Communications
  • Storage Solutions
  • Broadband Solutions
  • Switches/Routers
  • Base Stations
  • VOIP Solutions
  • Storage Processors

Consumer Electronics

  • Mobile Phones
  • Personal Computers
  • Portable Multimedia
  • Digital/Mobile TV
  • Set Top Boxes
  • Still/Video Cameras
  • Home Networking
  • GPS Systems

Safety/Mission Critical

  • Airplane Electronics
  • Automotive Control
  • Medical Control
  • Satellite Systems
  • Mil/Aero Solutions
  • Industrial Electronics

White Papers

Mentor Graphics has a large library of in-depth technical papers that you can download at your leisure. View FV White Papers

Using Assertions to Satisfy Elemental Analysis

This paper discusses DO-254 and what it requires for verification (including advanced methods for DAL A/B designs), explains the original intent of Elemental Analysis, the way it is typically satisfied... View White Paper

Virtual Devices for Protocol-Specific Host and Peripheral Interfaces

This paper provides a brief genealogy of virtual devices, describes their characteristics and benefits, and presents two design applications that demonstrate its utility and effectiveness. View White Paper

Understanding electronic IP: common issues and how to find them

Using IP blocks in designs requiring DO-254 compliance is becoming more popular as a way to reduce costs and schedules. However, the use of IP comes with its own problems and pitfalls. A good methodology... View White Paper

Verification Horizons Blog

Dave Rich Featured on EEWeb

Verification Horizons BLOG

I’m sure many of you know my colleague, Dave Rich. I’ve known Dave since our days at Co-Design Automation when we worked together defining the Superlog language, which eventually became SystemVerilog after…View Blog Post

How Did I Get Here?

Verification Horizons BLOG

Remembering Don Loughry “How did you get involved in standards,” I was asked. On a business trip to India in 2009, I was asked to come by the Mentor office in Noida to meet with some “freshers” and other…View Blog Post

Expanding the Verification Academy!

Verification Horizons BLOG

The philosophy behind our Verification Academy is to provide a comprehensive resource for evolving and maturing your functional verification process skills. We believe that each step an organization takes…View Blog Post

MultiMedia

Our rich set of recorded webinars and product demonstrations can help you be more successful with our products. Multimedia

UVM Debug

Making Hardware/Software Co-Verification Easier for ARM Cortex™-A Series Processor-based Designs

UVM Connect

News and Press

Solutions

Low Power Solutions

The Unified Power Format (UPF) provides the backbone to our low power technologies so engineers can define power based architectures, create power aware strategies, and verify low power designs throughout the TLM to GDSII flow. Low Power Solutions