Assertion-Based Verification

  • Assertions detect design errors at their source greatly increasing observability and decreasing debug time 
  • Assertions actively monitor a design (or testbench) to ensure correct functional behavior 
  • Questa supports SystemVerilog and PSL assertions - manually written or via OVL. Both standard languages can be used with either VHDL or SystemVerilog designs and testbenches 
  • Questa accelerates ABV adoption by providing Questa Verification Library (QVL), a library of pre-defined and pre-verified assertion checkers and standard interface protocol monitors.
  • 0-In CheckerWare Compiler enhances ABV productivity through a number of assertion management capabilities along with a comprehensive library of assertion macros and monitors, supporting any Verilog simulation environment.
  • Assertion and functional coverage are integrated in a single database with a single GUI for viewing and reporting

* AMCC standardizes on Systemverilog, Questa and AVM...read press release

* Newly updated: Advanced Verification Methodology Cookbook for SystemVerilog & SystemC...download the kit.


Assertion Based Verification Chart

Products

  • Questa AFV (Advanced Functional Verification)

    Questa is Mentor Graphic's Advanced Verification Environment and is the only integrated verification platform that can improve quality, productivity, and predictability for any verification flow.

  • Questa SV (SystemVerilog)

    The first SystemVerilog, single-kernel verification environment with a constraint solver, an assertion engine, a library of assertion checkers and monitors, functional coverage and a common user interface. Questa SV also provides a complete SystemVerilog design environment and built-in support for testbench automation (TBA), coverage-driven verification (CDV), and assertion-based verification (ABV).

  • 0-In Formal Verification
    The 0-In Formal Verification solution is easy to use and provides value throughout the design cycle - from block-level design, where it replaces traditional block-level simulation test benches, to chip-level design, where it replaces extensive pseudo-random simulation. 0-In Formal Verification integrates the industry's most powerful static and dynamic formal verification technologies with the industry's most comprehensive assertion-based verification (ABV) solution, enabling users to achieve functional verification closure quickly and predictably.
  • 0-In® Clock-Domain Crossing (CDC)
    0-In CDC is the industry's most comprehensive and easy-to-use Clock-Domain Crossing verification solution, integrating advanced verification engines with engineered methodologies. Using 0-In CDC, customers can efficiently and effectively eliminate all clock-domain crossing problems from their designs.
  • 0-In® CheckerWare® Compiler
    0-In CheckerWare Compiler accelerates ABV adoption and improves ABV productivity. By combining the industry's most comprehensive library of assertion macros and standard interface protocol monitors with assertion management capabilities, CheckerWare Compiler enables you to reach verification closure more efficiently and more effectively. The result is a complete assertion solution that delivers significant risk reduction and rapid return on investment.
© Mentor Graphics Corp. All rights reserved.