Products

0-In® Clock-Domain Crossing (CDC)

Designers increasingly use advanced multi-clocking architectures to meet the high-performance and low-power requirements of their chips. Inherent to these architectures are clock domain crossing (CDC) issues that go beyond the scope of current simulation-based verification techniques and require targeted verification solutions.

The 0-In® CDC verification solution sets the industry benchmark by providing the three essential elements for a complete CDC verification solution: structural or static CDC analysis, CDC protocol verification, and CDC reconvergence verification. It is the only solution that gives you confidence that all your CDC bugs will be found and expensive respins avoided.

Benefits

Immediate productivity. 0-In CDC automatically identifies your clock and clock distribution strategy, minimizing set up time.
Testbench free. Simply read in your RTL design, and 0-In CDC will pinpoint all potential CDC issues.
Most accurate reporting. Fewest false positives in the industry, so you don’t waste time chasing non-issues.
Fast identification and resolution of all issues. CDC-centric analysis and debug GUI leverages familiar schematics and waveforms where appropriate.
Flexibility. Fully leverage your existing verification infrastructure and testbenches to ensure maximum productivity.
Most comprehensive debug. Patented, automated metastability injection is the only way to find complex CDC reconvergence bugs.
Verification management. Automatic coverage reporting for CDC protocol and reconvergence verification enables you to effectively manage the overall verification process.

Products

0-In® Clock-Domain Crossing (CDC)

Benefits

SV Technical Resources

Product Resources

Other Resources

Featured Articles, News, Events

Eliminating Clock-Domain Crossing Bugs with 0-In CDC

Asynchronous clocks prove tough for verification

A Comparison of Metastability Modeling Methods

Simulation falls short with asynchronous clocks

Mentor 0-in vs. Atrenta Spyglass CDC

Five Steps to Quality CDC Verification

Clock domain Crossing Verification Made Easy (page 10)

Staying in sync

Multi-clock design without risk

Mentor Graphics Delivers Enhanced 0-In Clock Domain Crossing and Formal Verification Technology

Keeping time with clock domain crossings in FPGA's