Questa SV (SystemVerilog)
Questa is Mentor Graphic's Advanced Verification Environment and is the only integrated verification platform that can improve quality, productivity, and predictability for any verification flow.
Features
- Advanced functional verification technology: constrained-random, functional coverage, assertions
- Advanced Verification Methodology (AVM)
- Unified coverage database
- Integrated debug and analysis
- SystemVerilog, SystemC, Verilog, VHDL, PSL
- Questa Verification Library (QVL)
- TCL/tk
- 32 and 64-bit platform support - Solaris, Linux, Windows
Benefits
- Standards-based solution to support all flows, secure your verification investment, and enable interoperability
- AVM provides structure for quickly building verification environments that are reusable and exploit all the verification capabilities available in Questa
- Open source AVM is 100% SystemVerilog and SystemC delivering verification code portability
- QVL enables easy assertion adoption with common RTL structure checks and monitors for many standard bus protocols
- High-performance, multi-lingual engine for large regression suites
- Highly productive advanced verification and debug solution with built-in verification management for large, complex electronic systems
- Fast time-to-debug through assertions and multi-abstraction debug environment
- Constrained-random stimulus generation automates testing
- Verification management integrates coverage-driven verification plan closure with the verification process
- Power-aware simulation verifies low power designs
- Codelink option enables concurrent software/hardware verification and debug
- Seamless language interoperability facilitates integration of design & verification IP