Questa Power-Aware Simulation

• In-Depth

• Technical Publication: Low Power Design and Verification Techniques
• Featured Demo: Advanced Verification Methodology Session Seminar

The demand for high-performance, battery-operated SoCs and the need to reduce heat dissipation and energy consumption in non-portable systems has raised power as the number one design constraint. At process nodes below 100 nm, static energy loss surpasses dynamic power consumption as the primary power management concern. Consequently, static power management techniques such as multi-voltage, dynamic frequency and voltage scaling and power gating have become common place. Incorporation of these power management techniques introduces new functional verification challenges.

Early adopters of power gating design techniques verified the low power design late in the process – after physical design. Thus, low power design verification was burdened with all the issues of full-timing, gate-level simulation – slow simulations, long debug identification, and long resolution times. Many chips required re-spin as low power design bugs escaped to silicon. Questa’s Power Aware (PA) simulation provides the ability to verify low power design functionality at the RTL. Questa PA simulation has been proven on taped-out systems-on-chip designs for mobile handsets.

Questa’s Power Configuration File format formed part of the foundation for the industry standard Unified Power Format (UPF) developed by Accellera and in process of becoming an IEEE standard (P1801).

Benefits

• Early verification of low power designs
  Operating at the RTL results in early identification of functional issues when the low power design intent is mapped onto the design’s functionality.
• Side file format
  Specification of the low power design intent is captured separate from the HDL code facilitating RTL block reuse and independent changes in the low power design specifics.
• Standard design format – UPF*
  Questa PA simulation supports the industry standard Unified Power Format ensuring portability and interoperability of your design data.
• Verification of power gating
  Ensure design works correctly when power domains are shutdown by matching simulation behavior to hardware shutdown behavior.
• Accurate retention modeling
  Inferencing of registers and their control signals automates the mapping to retention register models.  Retention registers are modeled at RTL for high performance and accuracy in relationship to the priority of control signals – e.g., reset active when restore is active – and retention behavior, e.g., is the clock required to be gated low during retention.
• Flexibility
  User-defined corruption extent in power gating situations and signal- and process-level granularity provides flexibility in reusing hard macros and power-aware memory models.
• Easy use model
  Same Questa compile-optimize-simulate tool flow.  Simply specify the PCF or UPF design file(s) on the vopt (optimize step) command line.

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