Complex Analog/Mixed-Signal System-on-Chip Designs
Questa ADMS gives designers a comprehensive environment for verifying complex analog/mixed-signal System-on-Chip designs. ADMS combines four high performance simulation engines in one efficient tool: Eldo® for general purpose analog simulations, Questa® for digital simulations, ADiT™ for fast transistor-level simulations and Eldo RF for modulated steady state simulation.
Analog and mixed-signal SoC designs combine analog and digital content more tightly than ever before. They increasingly depend on integrated analog blocks such as A to D and D to A converters, phase-locked loops, and adaptive filters. This increased level of integration puts tremendous pressure on designers. Traditional design tool flows force designers to develop analog and digital subsystems in isolation, delaying the integration of these components until IC layout and the testing until after fabrication. Before Questa ADMS, AMS SoC design was a slow, expensive and error-prone process.
High Performance and Capacity Analog and Mixed-Signal Simulation
Questa ADMS extends the familiar Questa verification platform with analog and mixed-signal standard languages while maintaining a unified simulation environment. ADMS is language neutral; you can combine VHDL-AMS, Verilog-AMS, VHDL, Verilog, SystemVerilog, SPICE and SystemC anywhere and at any level in the design.
Questa ADMS includes the versatile EZwave mixed-signal waveform viewer and waveform calculation tool for display and analysis of mixed-signal results.
ADMS integrates with Mentor Graphics Pyxis Schematic by combining advanced model registration and selection with the DA-IC simulation cockpit and Mentor's high-speed hierarchical netlister. Pyxis Schematic is quick and easy to learn and integrates seamlessly with the other tools in Mentor's Custom IC Design Flow.
ADMS integrates into the Cadence Virtuoso Analog Design Environment with the same look and feel as any simulator inside the environment, but gives designers the advantage of ADMS analysis, commands and options. An enhanced symbol library providing specific Eldo devices is compatible with the Cadence library.
ADMS is the simulation engine underlying Mentor Graphics HyperLynx Analog for functional verification of complete printed circuit boards. A single schematic supports both PCB layout and functional analysis. HyperLynx Analog combines with HyperLynx Signal Integrity to extract parasitic PCB trace models for comprehensive board-level functional analysis. .
- Enables top-down design and bottom-up verification of multi-million gate AMS SoC designs.
- Lets designers combine language and simulation algorithms to fit the task
- Universally accepts IP written in any of the standard design languages for easy migration
- Builds on previous design investments through its design flow integration with Mentor Graphics Design Architect IC and Cadence Analog Design Environment
- Empowers high-level, system-level design, architectural exploration, and rapid learning of behavioral modeling techniques
The Questa® Advanced Simulator combines high performance and capacity simulation with unified advanced debug capabilities for the most complete native support of Verilog, SystemVerilog, VHDL, SystemC, PSL and UPF
ADiT is a fast-SPICE simulation tool that delivers the ability to obtain accurate and reliable simulation results 10X – 100X faster than traditional SPICE tools.
When accuracy matters designers choose Eldo Classic, Mentor’s “golden” SPICE accurate circuit simulator, designed to address the complex needs of analog and mixed-signal designers.
Eldo RF : Transistor-level simulator for RF IC designs.
Pyxis Schematic, part of Mentor's Pyxis Custom IC Design Platform, provides a powerful and easy-to-use design entry environment with advanced capabilities that boost designer productivity.
ICanalyst is an advanced analog, RF and mixed-signal verification environment for custom IC design. ICanalyst manages the validation of custom analog ICs though process-variation, using specification-driven methodology to fully characterize design figure of merits and let you optimize design to improve yield.