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Verification Horizons Blog

26 Feb, 2015

Gordon Allan A colleague recently asked me: Has anything changed? Do design teams tape-out nowadays without GLS (Gate-Level Simulation)? And if so, does their silicon actually work? In his day (and mine), teams prepared in 3 phases: hierarchical gate-level netlist to weed out X-propagation issues, then full chip-level gate simulation (unit delay) to come out of reset and exercise all I/Os, and weed out any other … Read More

23 Feb, 2015

Harry Foster It’s my favorite time of year again—DVCon!  And I believe that the DVCon 2015 technical program committee has put together one of the technically best DVCon’s in years. In this blog I plan on highlighting a few DVCon events that you might want to put on your calendar. First, at this year’s conference the Verification Academy has a dedicated booth (#301), and I hope you stop by to say hello to myself, … Read More

19 Feb, 2015

Portable Stimulus at DVCon

Posted by Matthew Ballance

Matthew Ballance It’s amazing how quickly a year goes by. DVCon 2014 seems like it was just a few months ago, and here we are rolling up on DVCon 2015. As my colleague Dennis Brophy blogged earlier, it was just a year ago that Mentor Graphics proposed that Accellera launch a Proposed Working Group (PWG) to explore whether sufficient need and interest existed in the industry to standardize a portable stimulus specification. … Read More

11 Feb, 2015

Dennis Brophy Accellera Approves Creation of Portable Stimulus Working Group At DVCon 2014, Mentor Graphics proposed Accellera launch an exploratory exercise, called a Proposed Working Group (PWG), to determine if there was sufficient interest and need to create a standard in this area.  To help motivate the consideration of this activity, we indicated we would offer our graph-based test specification embodied in … Read More

8 Feb, 2015

Harry Foster FPGA Design Trends In my previous blog, I introduced the 2014 Wilson Research Group Functional Verification Study (click here). The objective of my previous blog was to provide an overview on our large, worldwide industry study. The key findings from this study will be presented in a set of upcoming blogs. In this blog, I present trends related to various aspects of FPGA design to illustrate growing … Read More

21 Jan, 2015

Harry Foster This blog is a continuation of a series of blogs that present the highlights from the 2014 Wilson Research Group Functional Verification Study (for a background on the study, click here). In this blog I discuss the issue of study bias, and what we did to address these concerns. MINIMIZING STUDY BIAS When architecting a study, three main concerns must be addressed to ensure valid results: sample validity … Read More

21 Jan, 2015

Harry Foster This is the first in a series of blogs that presents the findings from our new 2014 Wilson Research Group Functional Verification Study. However, unlike my previous Wilson Research Group functional verification study blogs, which focused on the ASIC/IC market, I plan to begin this set of blogs with an exclusive focus on FPGA trends. Why? For the following reasons: Unlike the traditional ASIC/IC market, … Read More

14 Jan, 2015

Who Knew VIP?

Posted by Mark Olen

Mark Olen “Who Knew?” about verification IP (VIP), was the theme of a recent DeepChip post by John Cooley on December 18.  More specifically the article states, “Who knew VIP was big and that Wally had a good piece of it?”  We knew. We knew that ASIC and FPGA design engineers can choose to buy design IP from several alternative sources or build their own, but that does not help with the problem of verification.  … Read More

6 Jan, 2015

Joe Hupcey III 2014 was an exciting year for formal verification to say the least, and below I call out a sampling of noteworthy conference papers that contributed to this energy. Specifically, they show how formal property checking itself is simultaneously scaling to tackle ever larger verification problems, and also being extended to cover domains that were once exclusively the province of simulation. ———- Conference: … Read More

12 Dec, 2014

Tom Fitzpatrick Just in time for Christmas and other year-end holidays, I am pleased to announce that the latest issue of Verification Horizons is now available on-line. As usual, we have a great lineup of articles that I’m sure you’ll find informative: Integrate Ethernet QVIP in a Few Hours: an A-to-Z Guide - Shows how to instantiate a Questa VIP (QVIP) component quickly and easily into your UVM environment, … Read More

24 Nov, 2014

Rich Edelman SystemVerilog Testbench Debug – Are we having fun yet? Fun Debug should be fun. Watching waveforms march by, seeing ERRORS and WARNINGS pop out in a transcript file, tracing drivers back to their source, understanding race conditions between simulators and between source code changes – and my favorite – debugging random stability issues. Fun. Old School – logfiles and interactive Or at least it … Read More

17 Nov, 2014

Joe Hupcey III Few verification tasks are more challenging than trying to achieve code coverage goals for a complex system that, by design, has numerous layers of configuration options and modes of operation.  When the verification effort gets underway and the coverage holes start appearing, even the most creative and thorough UVM testbench architect can be bogged down devising new tests – either constrained-random … Read More

5 Nov, 2014

Matthew Ballance Between 2006 and 2014, the average number of IPs integrated into an advanced SoC increased from about 30 to over 120. In the same period, the average number of embedded processors found in an advanced SoC increased from one to as many as 20. However, increased design size is only one dimension of the growing verification complexity challenge. Beyond this growing-functionality phenomenon are new layers … Read More

5 Nov, 2014

On-Demand Webinar: UVM Sequences in Depth

Posted by Tom Fitzpatrick

Tom Fitzpatrick When I was at DAC this year, I had a few folks come up to me at our Verification Academy booth and suggest that I do a “Recipe of the Month” webinar on UVM sequences. They’d seen plenty of information on sequence mechanics and generating stimulus with sequences, but these users were particularly interested in Slave sequences, which aren’t necessarily very intuitive. Of course, … Read More

9 Oct, 2014

DVCon India: A Smashing Hit!

Posted by Dennis Brophy

Dennis Brophy DVCon India, held in September 2014 in Bangalore, built on the Indian SystemC User Group meeting events and added a Design & Verification track to its popular system-level design (ESL) track that has been popular for many years.  The main stage played host to the keynote presentations, opening ceremonies and best paper and poster awards. Several DVCon India keynote presentations, which I will go … Read More

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