I’m sure many of you know my colleague, Dave Rich. I’ve known Dave since our days at Co-Design Automation when we worked together defining the Superlog language, which eventually became SystemVerilog after being donated to Accellera. Hard to believe that was 11 years ago. Having gotten to know Dave as a friend as well as a colleague over that time, I really enjoyed learning even more about him in his … Read More
Remembering Don Loughry
“How did you get involved in standards,” I was asked.
On a business trip to India in 2009, I was asked to come by the Mentor office in Noida to meet with some “freshers” and other participants in Mentor’s Displaced Worker Program who were in the middle of a SystemVerilog training. As one of many who have been engaged in the development of the SystemVerilog (aka IEEE Std 1800™-2009) … Read More
Tags: UC Davis, Don Loughry, 488, HP-IB, Lan, Ethernet, Hewlett-Packard
The philosophy behind our Verification Academy is to provide a comprehensive resource for evolving and maturing your functional verification process skills. We believe that each step an organization takes in evolving verification skills should have measurable results and benefits. With that in mind, I am excited to announce two new modules we are adding to the Verification Academy: UVM Express and Advanced … Read More
Tags: Verification Academy, UVM
Advanced verification techniques including functional coverage and constrained random stimulus generation have proven themselves invaluable in the design of the smallest FPGAs to the largest SoCs today. Still many design and verification teams that need to and are willing to embrace these technologies have yet to do so. Verification environments written with basic hardware description languages like … Read More
In his recent post on UVM: Some Thoughts Before DVCon, Dennis outlined some great ideas about what we think should happen next for UVM. His 3rd point, “UVM needs to bridge the system domain,” is particularly relevant given the newly-formed Accellera Systems Initiative. This is actually an area we’ve been contemplating for a while here at Mentor, and as Dennis indicated, we shared our thoughts on this … Read More
Tags: Verification Methodology, Verification Academy, Functional Verification, SystemC, DVCon, UVM Connect, UVM-1.1, UVM
Is my car trying to tell me something?
This past Friday was the beginning of a two day internal functional verification meeting at Mentor Graphics corporate headquarters on Intelligent Testbench Automation (iTBA). (Mentor’s iTBA product, Questa inFact is hot and getting hotter.) After getting to my car to return home at the end of the first day, I was thinking that the large interest in this technology … Read More
Tags: UVM, Tipping Point, Veloce, inFact, Intelligent Testbench Automation, Crossing the Chasam, Questa, SoC, iTBA, OVM
It is time to talk about what happens next with UVM
The Design and Verification Conference (DVCon) has become the premier event to discuss front-end design issues with an emphasis on verification. If one listens to the Conversation Central interview of DVCon leadership it is clear how singularly important DVCon is. As one of the three organizers of the UVM Tutorial on Monday, I know the conference … Read More
Tags: DATE Conference, DVCon, Accellera, UVM, SystemC
“Ready, Set, Deploy”
The last half year has seen a theme from Accellera Systems Initiative that declares its Universal Verification Methodology (UVM) is ready for design and verification teams to adopt. This theme started with a whitepaper from Accellera I authored with two of my peers, Stan Krolikoski from Cadence Design Systems and Yatin Trivedi from Synopsys. A day long UVM tutorial will be featured … Read More
IEEE Std. 1666™-2011 Available as Free Download
In November 2011 I blogged the IEEE Standards Association (SA) approved a revision to the popular SystemC standard, known officially as IEEE Std. 1666™-2011. One of the key elements of this standard includes the addition of Transaction Level Modeling (TLM). I pointed to several online resources to learn more about the revised SystemC standard in that … Read More
I think very few engineers would argue with the claim that the longer a bug goes undetected, the more expensive it is to fix. In fact, the general rule-of-thumb is that the cost to fix a bug increases by an order of magnitude as a project progresses from one milestone to the next. Bugs found before simulation obviously have the lowest cost. Bugs found at block or subsystem simulation are generally easier … Read More
