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10 Apr, 2014

Dennis Brophy Its always fun to take the wraps off of solutions we have been hard at work developing.  The global team of Mentor Graphics engineers have spent considerable time and energy to bring the next level of SoC design and verification productivity to what seems to be a never ending response to Moore’s Law.  As silicon feature sizes get smaller, design sizes get larger and the verification problem mushrooms.  … Read More

UPF, UVM, Codelink, Enterprise Verification Platform, Accellera, Portable Stimulus, VirtuaLAB, Gary Smith EDA, Moore's Law

17 Mar, 2014

New Verification Academy ABV Course

Posted by Harry Foster

Harry Foster As some of you might be aware, the Verification Academy has a video course dedicated to the topic of Assertion-Based Verification (ABV). In fact, this was the first video course we released for the academy almost six years ago. To date, it has remained one of our most popular courses. Yet one of the most common requests for improvement to this course has been adding content that focuses more on the … Read More

3 Mar, 2014

Tom Fitzpatrick DVCon is always one of my favorite events in our industry, and I am proud to let you know that the latest issue of Verification Horizons is available “hot off the presses” at the Verification Academy to mark the occasion. For those of you attending the conference, please consider this issue as an addendum to the great technical program being offered (especially paper 8.1, “Of Camels and Committees: … Read More

UVM, Verification Academy, DVCon, Verification Horizons

27 Feb, 2014

DVCon–The FREE Side

Posted by Dennis Brophy

Dennis Brophy Psst!  I’ll let you in on some news… While DVCon calls the free portion of the conference “Exhibits Only,” let me share a little secret for you – You also gain access to the conference panels and the keynote presentation. For those in Silicon Valley and local to DVCon, I invite you to register for the FREE side of the conference, not just for the conference exhibition that will have (in evening hours) … Read More

Software, Verification, DVCon, Verification Gap

25 Feb, 2014

More DVCon–More Mentor Tutorials!

Posted by Dennis Brophy

Dennis Brophy As DVCon expands, we at Mentor Graphics have grown our sponsored sessions as well.  Would you expect less? In DVCon’s recent past, it was a tradition for the North American SystemC User Group (NASCUG) to sponsor a day of activity before the official start of the conference.  When OSCI merged with Accellera, the day before the official conference start grew to become Accellera Day with a broader set … Read More

DVCon, Emulation, Accellera, SystemC, Formal Verification, fpga prototype

23 Feb, 2014

UVM 1.2: Open Public Review

Posted by Dennis Brophy

Dennis Brophy UVM 1.2 Release is Imminent As vice chair of DVCon 2014, I can share with you that the Universal Verification Methodology (UVM) remains a topic of great interest.  It sets the pace for tutorials and given the pending release by Accellera, learning what is new in UVM 1.2 is a compelling reason to attend DVCon. The Accellera Day tutorial series on Monday at DVCon is popular with UVM being a session of … Read More

DVClub, DVCon, Accellera, Universal Verification Methodology, UVM 1.2, Git, OSCI

11 Feb, 2014

DVCon 2014: Standards on Display

Posted by Dennis Brophy

Dennis Brophy One of the nice things about DVCon is the update one can get from the developers of IEEE and Accellera standards.  And this year’s DVCon is no exception.  The four days of DVCon begin and end with tutorials that cover updates to popular standards like UVM, UPF, SystemC and more.  For our part, Mentor Graphics is participating in the development and delivery of these updates with our peers. I have written … Read More

IEEE 1801, DVCon, UVM, SystemC, UPF

4 Feb, 2014

Joe Rodriguez Marketing teams at FPGA vendors have been busy as the silicon nanometer geometry race escalates. Altera is “delivering the unimaginable” while Xilinx is offering “all programmable SoCs” to design centers. It’s clear that the SoC has become more accessible to a broader market today and that FPGA vendors have staked out a solid technology roadmap for the near future. Do marketing … Read More

Verilog, Verification, VHDL, Code Coverage, Coverage, Assertions, FPGA, Functional Verification

6 Jan, 2014

Dennis Brophy The UCIS Story There is no secret as design sizes grow it is doubly burdensome for verification.  Two factors that are easy to measure is the time it takes to simulate a design and the other is the size of the dataset that contains the results of the verification runs. Simulation times are growing and the datasets are getting larger.  While time and attention is given to accelerated verification through … Read More

Coverage Closure, DVClub, Accellera, UCIS, Unified Coverage Interoperability Standard, Metrics

28 Nov, 2013

Harry Foster Wow! I’ve been on the road since August, and finally found a spare moment to get back to this blog. I started this blog series with a prologue that gave a little bit of background on the 2012 Wilson Research Group study. And with this epilogue, I will draw the series to a conclusion with some insight on the study process. Many people believe that industry studies in general (and particularly ones … Read More

15 Nov, 2013

New Verification Horizons Issue Available

Posted by Tom Fitzpatrick

Tom Fitzpatrick Wanted to let you all know that the October, 2013 issue of Verification Horizons is available online. You can view the articles or download the issue here. In addition to a little paternal bragging in the Introduction, I wanted to call your attention in particular to a few of the articles written by some Mentor colleagues: Software-Driven Testing of AXI Bus in a Dual Core ARM System by Mark Olen, Mentor … Read More

30 Oct, 2013

Mark Olen MENTOR GRAPHICS AT ARM TECHCON This week ARM® TechCon® 2013 is being held at the Santa Clara Convention Center from Tuesday October 29 through Thursday October 31st, but don’t worry, there’s nothing to be scared about.  The theme is “Where Intelligence Counts”, and in fact as a platinum sponsor of the event, Mentor Graphics is excited to present no less than ten technical and training sessions about … Read More

testbench, SoC, Verification, Formal Verification, functional coverage, ARM, Verification Academy, iTBA, Functional Verification, Intelligent Testbench Automation

15 Oct, 2013

Dennis Brophy Low Power Flow Kicks-off Symposium In the world of electronic design automation, as an idea takes hold and works its way from thought to silicon, numerous tools are used by engineers and the like to help bring a good idea to product fruition.  Standards play a key and important role to help move your user information from high-level concepts into the netlists can be realized in silicon.  The IEEE Standards … Read More

UPF, IEEE 1801, ieee standards association, ARM, Questa Vanguard Partnership, Interoperability, Low Power

4 Oct, 2013

Harry Foster We are truly living in the age of SoC design, where 78 percent of all designs today contain one or more embedded processors.  In fact, 56 percent of all designs contain two or more embedded processors, which brings a whole new level of verification challenges—requiring unique solutions. A great example of this is STMicroelectronics who recently shared their experience and solution in addressing verification … Read More

OVM, Emulation, UVM, SystemC

19 Sep, 2013

Dave Rich It’s hard for me to believe that SystemVerilog 3.1 was released just over 10 years ago. The 3.1 version added Object-Oriented Programming features for testbench development to a language predominately used for RTL design synthesis. Making debug easier was one of the driving forces in unifying testbench and design features into a single language. The semantics for evaluating expressions and executing … Read More

Accellera, testbench, Verification

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