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Verification Horizons Blog

12 Dec, 2014

Tom Fitzpatrick Just in time for Christmas and other year-end holidays, I am pleased to announce that the latest issue of Verification Horizons is now available on-line. As usual, we have a great lineup of articles that I’m sure you’ll find informative: Integrate Ethernet QVIP in a Few Hours: an A-to-Z Guide - Shows how to instantiate a Questa VIP (QVIP) component quickly and easily into your UVM environment, … Read More

24 Nov, 2014

Rich Edelman SystemVerilog Testbench Debug – Are we having fun yet? Fun Debug should be fun. Watching waveforms march by, seeing ERRORS and WARNINGS pop out in a transcript file, tracing drivers back to their source, understanding race conditions between simulators and between source code changes – and my favorite – debugging random stability issues. Fun. Old School – logfiles and interactive Or at least it … Read More

17 Nov, 2014

Joe Hupcey III Few verification tasks are more challenging than trying to achieve code coverage goals for a complex system that, by design, has numerous layers of configuration options and modes of operation.  When the verification effort gets underway and the coverage holes start appearing, even the most creative and thorough UVM testbench architect can be bogged down devising new tests – either constrained-random … Read More

5 Nov, 2014

Matthew Ballance Between 2006 and 2014, the average number of IPs integrated into an advanced SoC increased from about 30 to over 120. In the same period, the average number of embedded processors found in an advanced SoC increased from one to as many as 20. However, increased design size is only one dimension of the growing verification complexity challenge. Beyond this growing-functionality phenomenon are new layers … Read More

5 Nov, 2014

On-Demand Webinar: UVM Sequences in Depth

Posted by Tom Fitzpatrick

Tom Fitzpatrick When I was at DAC this year, I had a few folks come up to me at our Verification Academy booth and suggest that I do a “Recipe of the Month” webinar on UVM sequences. They’d seen plenty of information on sequence mechanics and generating stimulus with sequences, but these users were particularly interested in Slave sequences, which aren’t necessarily very intuitive. Of course, … Read More

9 Oct, 2014

DVCon India: A Smashing Hit!

Posted by Dennis Brophy

Dennis Brophy DVCon India, held in September 2014 in Bangalore, built on the Indian SystemC User Group meeting events and added a Design & Verification track to its popular system-level design (ESL) track that has been popular for many years.  The main stage played host to the keynote presentations, opening ceremonies and best paper and poster awards. Several DVCon India keynote presentations, which I will go … Read More

12 Sep, 2014

Matthew Ballance Verification engineers spend lots of time creating tests. In fact, creating enough tests to verify the design functionality consistently tops the list of verification challenges, according to periodic surveys of our customers. Top Verification Challenges One challenge in test creation is that verification occurs in multiple environments. For high-level models, verification might be performed in a SystemC … Read More

11 Sep, 2014

Supporting A Season of Learning

Posted by Dennis Brophy

Dennis Brophy From those just beginning to study electronic systems design to the practicing engineer, this is the time of the year when those taking their first steps to learn VHDL, Verilog/SystemVerilog join the academic “back to school” crowd and those who are using design & verification languages in practice are honing skills at industry events around the world. A new academic year has started and the Mentor … Read More

20 Aug, 2014

DVCon Goes Global!

Posted by Dennis Brophy

Dennis Brophy The ever popular Accellera Design & Verification Conference held annually in Silicon Valley is going global.  Accellera System Initiative has expanded many of its SystemC user group events to be more inclusive of other Accellera and IEEE standards.  In doing so, the local organizers of these events have moved to adopt the popular DVCon USA style to organize their events to include this large complement … Read More

12 Aug, 2014

Tom Fitzpatrick As some of you may have seen, we release a great DAC edition of Verification Horizons back in June. Unfortunately, we were so focused on preparing for a great Verification Academy Booth at DAC that I completely forgot to blog about the issue! Well, as the saying goes, “better late than never.”  In particular, I’d like to call your attention to two articles. The first is “Best … Read More

9 Jul, 2014

Accellera Approves UVM 1.2

Posted by Dennis Brophy

Dennis Brophy Accellera has announced the completion of a multi-year effort to update its latest edition of the Universal Verification Methodology (UVM).  In completing this effort, the UVM 1.2 Class Reference Document was approved as an Accellera standard and the UVM Working Group has supplied an accompanying open-source reference implementation.  Questa supports UVM 1.2. In addition to the resources you can download … Read More

29 May, 2014

Matthew Ballance Verification engineers put lots of effort into writing and tuning constraints for random stimulus. It’s critical that the constraints correctly express the valid relationships between the stimulus variables. Otherwise, invalid stimulus will be generated or, worse, important valid combinations of stimulus will not be generated. When it comes to bug hunting, running open-loop random stimulus is recognized … Read More

21 May, 2014

Matthew Ballance If there was a tool that enabled you to create tests 10x more productively that you can today, would you change your entire verification language and testbench environment tomorrow? Not likely. Despite our love of technology that makes us more productive and efficient, lots of thought and planning goes into making big shifts in verification methodology. Now, what if that same 10x boost in test creation … Read More

7 May, 2014

The FPGA Verification Window Is Open

Posted by Joe Rodriguez

Joe Rodriguez My Feb. 4 post introduced Mentor Graphics’ three-step FPGA verification process intended to help design teams get out of the reprogrammable lab more effectively. Since then, I’ve engaged FPGA vendors, design managers and engineers to explain the process, paying special attention to the merits and technical detail for injecting automation into any FPGA verification environment, the hallmark of Mentor’s … Read More

Verilog, Verification, VHDL, Code Coverage, Coverage, Assertions, FPGA, Functional Verification

25 Apr, 2014

UVM DVCon 2014 Tutorial Video Online

Posted by Dennis Brophy

Dennis Brophy DVCon 2014 Conference Proceedings Published With record attendance announced for DVCon 2014, one might wonder if there is really a need to put some of the “Accellera Day” tutorial videos online.  With more than 1,000 professionals attending in some capacity, it would be easy to conclude that everyone that needs to know about UVM and the developments on the updated version to it, probably know.  Looking … Read More

DVCon, Functional Verification, Accellera, UVM, register layer, stimulus generation

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