Emulation 102 – Emulation ROI – How can you not to invest in Emulation methodology?

Emulation 102 – Emulation ROI – How can you not to invest in Emulation methodology?

In my last blog I stated I was an evangelist for using emulation to verify SoC designs. I defined Emulation Systems as verification systems which provide (1) Vector and transaction-based simulation acceleration and (2) in-circuit emulation (ICE) capability to perform system integration and test using real world data before silicon is available. Emulation systems are typically built on custom emulation SoC’s which provide extremely fast compilation and place and route times, and provide full internal DUT visibility for debug, among other features.

What I have seen over the years in this business is that many companies believe without question in the benefits of emulation and use it extensively. However, many other companies never take the time to quantify the potential benefits of emulation on their development project schedules and costs. They look at emulation system costs as an incremental project expense without considering that they may actually reduce their project budgets and minimize much of their schedule risk by leveraging this methodology. Companies taking this latter view are likely to fall behind their competition which leverages emulation in their development processes to reduce costs and schedules.

Let me try to summarize the value emulation delivers in reducing costs and minimizing project schedule risk.

Everyone has a plan. But then there is THE PLAN that everyone truly believes is the real plan. Several studies have documented that about 80% of projects slip their Engineering schedules by 20% or more, and that the typical project can easily have 2-3 unplanned spins of silicon. While the costs of such slippage and additional silicon cycles are not budgeted, project after project has proven that they are real costs that can be expected on a SoC project.

So one can pretend the costs are not likely, and face the consequences, or one can look for ways to minimize the attendant project schedule and cost risks. Eliminating the engineering slippage risk to a project and eliminating a single unplanned silicon spin cycle can save millions of dollars of direct project expenses and easily justify adopting new methodologies and tools.

Experienced emulation users use emulation to reduce or eliminate just such risks. Emulation systems typically accelerate both signal level and transaction level verification by 1000 to 10,000x, depending on the environment and how it is used. That means block level tests taking a couple of days can often be run in an hour or so, and weeks of full chip testing can be done in hours.

I would not advocate that emulation replace simulation completely. However, if one begins accelerating block level tests mid-way in the block level RTL development process, and accelerates the majority of the full chip simulation runs with emulation systems, then the project time savings of simulation runs can be tremendous. This can greatly increase the efficiency of engineering by providing much faster feedback about problems in the design. There are also easily quantifiable attendant lower server and simulation license project cost reductions. Further, if one can take a fraction, say 20% of the time savings of tests to reduce project schedule, then you may be looking at many weeks of reduced project engineering costs – hardware and software engineering, project management, etc..

Every project has different design and development project profiles. But here’s an example.

Let’s look at a moderate chip development project of 20 million gates. Personnel expenses can easily cost $100,000 per week for 25-30 hardware and software engineers. A typical schedule, including the up front architectural phase would be in the 65 week range. Eliminate a 20% engineering slip on a one year project, you save $1.3M or more in personnel expenses. Dropping just one extra silicon spin, which from tapeout to validation can eliminates another 10+ weeks from the schedule, and you save another $1M in direct personnel expenses. Eliminate the mask set costs from the spin – save another $1M. $1M here, $1M there, and you start to look at real money, $3M so far and 20+ weeks of project risk taken out of the “real” project plan. Then you start adding in reductions in project allocated simulation license and server costs from being able to replace half of your block level simulation runs and most your full chip simulations with acceleration. Even with added costs for emulations systems and support, you might reasonably see 20 weeks schedule improvement and save a few million dollars in total costs.

We have not even looked at the business impact of shipping on time, or even ahead of schedule, which is what most emulation users report. For a true ROI, one should really consider the value of 20 weeks of added product shipments. Or the converse without emulation, the negative impact on product lifetime revenue of engineering slippage and the extra silicon spins.

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