Emulation 103--Accelerating Transaction-based Verification

Emulation 103--Accelerating Transaction-based Verification

Transaction-Based Verification is a technique for verifying modern SoC designs with interfaces such as PCI express, using test benches at the transaction level of abstraction. Transaction-based verification complements directed and constrained random tests, and is an emerging methodology for verifying complex SoCs that have multiple on-chip standard bus and peripheral interfaces. Typically in a transaction-based verification environment, the test bench is developed in C/C++, System C or System Verilog, and is used to drive data to the RTL design blocks of an IC’s design. The principal advantage of transaction-based tests is that they can be developed much more quickly than directed tests without needing in-depth knowledge of the protocol or the SoC, and can be re-used whenever the target standard is applied.

Most SoC development teams employ a variety of test development methods. Regardless of whether tests are directed, constrained random, or traffic generator oriented, as chip designs grow, the complexity of tests, and their run times grow exponentially.

In the old days (I date myself), even before emulation became available, simulation acceleration systems were used to overcome the long simulation run times. But these systems were targeted at what would be seen today as very small designs.

Early emulation systems did not have the high speed host interfaces or the efficient simulator APIs like SystemVerilog DPIs available today. The early emulation systems were largely used for system integration and test, post-RTL development. Often the use of emulation was limited by the time it took to map designs correctly, and it was in a race to show productivity before the first silicon was delivered. Today’s FPGA prototyping performs pretty much the same function, and often faces the same issue. As a consequence, to accommodate the ever increasing verification problem with large chip designs, the ‘farm” of simulation servers emerged the preferred RTL verification environment in the late 90’s and persists in most design environments today.

Over the last several years, simulation farms have run into limitations due to the overall complexity of the verification challenge and the finite ability to parallelize tests and a farm’s attendant power and cooling requirements. For the past several years, as new emulation technology emerged, the use of emulation systems for accelerating simulations has become its primary differentiation from FPGA-based prototyping systems. The principal value of such acceleration is to shorten the time to tapeout as many more verification cycles can be achieved in a much shorter period of time. Plus, the days and weeks of block and full chip simulation runs are typically reduced to minutes and hours, allowing bugs to be discovered faster and fixes verified in less time. The result is that much of the time savings can be applied to directly shorten schedules, and/or to remove some of the risk of slippage.

With the emergence of (1) transaction-based verification for critical portions of SoC design, (2) standards for communicating between host and DUT in emulation systems enabling interoperability with simulators, and (3) the widespread adoption of SystemVerilog for test benches, it is now possible to synthesize timed portions of transaction-based verification environment into emulators along with DUT to accelerate a large portion of the test bench with the DUT in an accelerated simulation using emulation systems. Critical to this type of operation is the availability of synthesis tools for the most crucial high-level System Verilog constructs. With all the old bottlenecks of co-simulation in the early emulation systems eliminated, in such an environment, accelerated transaction-based verification can be run at nearly full in-circuit emulation speeds.

As a result, what we see in the emulation space is that the traditional driver of getting a high speed platform for early software debug and system integration is now being displaced by the huge advantage of moving many of the simulation runs to an accelerated environment. And, with the increased ease of developing re-usable transaction-based test benches, transaction-based verification acceleration is quickly becoming a mainstream requirement for SoC development teams.

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