If there was a tool that enabled you to create tests 10x more productively that you can today, would you change your entire verification language and testbench environment tomorrow? Not likely. Despite our love of technology that makes us more productive and efficient, lots of thought and planning goes into making big shifts in verification methodology. Now, what if that same 10x boost in test creation productivity could be obtained by just bolting a new tool onto your existing verification language and environment?
Intelligent Testbench Automtion allows just such a boost in verification productivity while making only minor changes to your existing verification environment. In a UVM environment,the QuestainFacttechnology for iTBA imports and controls existing sequence items and configuration classes to achieve faster coverage closure and more-comprehensive testing. But, what about verification environments based on SystemC or VHDL? The good news is that Questa inFact can be bolted onto these environments with just a few lines of code.
Learn more about how Intelligent Testbench Automation integrates into a VHDL testbench environment in this article from the DVCon issue of Verification Horizons.
Do you use a SystemC or VHDL testbench for verification? How are you automating test creation in your verification process?