Time to Power Diet!
Time to Power Diet!
I always start the New Year thinking I should get in shape and lose a few pounds (That’s lbs not £ - I’d very much like to gain some £’s). The last couple of years the whole family has signed up for a local fun run that takes place in March. This creates that classic compelling event that means we have to get off the sofa and do a bit of training. Last year I was pleased that I managed to keep up with my 15 year old daughter (she’s in the running team at school) and even managed to finish within a few seconds of her. However, when I saw her time was actually a couple of minutes slower than the time she’d done the previous year when she’d been running with the school running team, I realised she was just “taking it easy” for my sake:-)
Of course, the alternative to burning fat by exercise is to consume less in the first place. Indeed consuming less power is the only choice for tomorrow’s consumer electronic products.
At the recent Silicon South West Power Down seminar Nick Flaherty explained how for flat panel TV manufacturers to continue to sell their products in the US they would have to reduce power consumption by around 25% for LCD and 40% for Plasma. Considering that most of the power is actually consumed by the display and driver circuits that leaves precious little for the demodulation and video processing.
At the same event, Ramses Valvekens, CEO, eAsics explained how implementing and verifying the ultra low power features of just the digital sections of their far field RF ID designs (marketed as TegoTag) turned a 2 week RTL design exercise that could probably be completed by a junior engineer into a 5 month, intensive, iterative design, analysis and verification task. One of the main challenges was the continual re-verification of the design against the C++ reference model as more & more power saving features were added to the design.
This brings me neatly to the topic of our next Tuesday Tech Talk, Power Aware Verification. One of our Verification Technologist, Gabriel Chidolue will explain how the IEEE 1801 UPF standard helps verification engineers be power aware. He may even tell us how to lose a few lbs and gain a few £’s and maybe I can keep up with daughter on the fun run in March.
About Steve Collis
My first exposure to Electronic Design Tools was at GEC Telecommunications where I manually entered HILO netlists using a DEC vt100 connected to a VAX to simulate a gate array design which eventually became part of a System X telephone exchange. Even though this was tedious work I could see the huge advantages in modelling a design in the computer verses trying to breadboard it in the lab. I was then lucky enough to be able to get involved in the development of early IC physical design system using parameterised language descriptions to build layouts of standard cells.
Later on when I worked at DEC, I was involved in the early wave of RTL design using early language based simulators and synthesis tools and worked on the development of an early VHDL simulator. This early exposure to RTL design brought me to Mentor Graphics where I was lucky enough to be involved the adoption of RTL based design techniques and the significant changes to Gate Array, Asic, SoC and FPGA design techniques that have taken place over the last 20 years or so. More recently I have held various consulting and management positions and today head up a team of product specialist concentrating on high level design and functional verification across Europe.
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