The latest revision of the IEEE 1800-2012 SystemVerilog Language Reference Manual (LRM) is about to hit the presses; though I doubt people will be printing the 1300+ pages on their own from the soon to be readily available online version. Here’s a little background into what’s in all those pages.
The first SystemVerilog LRM came from Accellera in 2002 as a set of extensions to the IEEE … Read More
VHDL-2008 Explained Via 7 Course Modules
For some time now a dedicated group of engineers have defined and standardized an important update to the VHDL standard. Also know as IEEE Std. 1076™-2008, this update to VHDL took an interesting path to get to where it is today. The VHDL standards team started the standards development work in the IEEE but sought additional input and standards project funding … Read More
IEEE Std. 1800™-2012 Officially Ratified
The IEEE Standards Association (SA) Standards Board (SASB) officially approved the latest SystemVerilog revision, Draft 6, as an IEEE standard. The SASB Review Committee (RevCom) agenda and the SASB agenda include review and formal approval of the latest work by the IEEE Computer Society Design Automation Standards Committee’s (DASC) SystemVerilog Working Group … Read More
Muttiple Inheritance, RevCom, Assertions, Tom Fitzpatrick, UVM, Ben Cohen, Soft Constraints, Hard Constraints, IEEE SASB, Stu Sutherland, DASC, DVCon
Verification Academy Adds Major New Technical Resource
The Verification Academy adds another major methodology cookbook to focus on effective coverage adoption. The Coverage Cookbook describes the different types of coverage that are available to track your verification process progress, how to create a functional coverage model from a specification, and provides examples to implement functional … Read More
OVM, UCDB, Coverage, Coverage Closure, Accellera, UCIS, Harry Foster, UVM, IEEE 1800, Coverage Cookbook, Verification Academy, functional coverage
Ready for 100 billion “things” connected by the Internet?
The IEEE Standards Association (SA) Corporate Advisory Group (CAG) has been working to bring industry input into the standards development organization on the emerging Internet of Things (IoT) trend that will connect billions of devices with each other.
As you can imagine, the impact this will have to the service structure down to the development … Read More
Hi Everyone,
Just wanted to let you know that the latest and greatest edition of Verification Horizons is now available. The articles in this issue all discuss how you can apply new techniques and technology to achieve greater verification productivity. And for you football (I mean “American football” as opposed to “soccer”) fans out there, be sure and check out the Editor’s … Read More
When it comes to formal methods, many engineers are skeptics. Perhaps this is due to value propositions that have been pitched over the years that have over-promised yet under-delivered in terms of results. Or perhaps it is due to the advanced skills that have traditionally been required to achieve predictable and reliable results. After all, historically this was the case—dating back to the mid-nineties … Read More
A new style takes center stage
It was Fashion Week in Portland, Oregon in early October. And while the thought of Portland and fashion might not be believable to many in the world, especially those who look to the design houses of Paris or Milan, it was. What struck me was the blend of fashion with high tech this year. Intel took the opportunity to roll out its fashion inspired campaign (dressing … Read More
At the 2012 Design Automation Conference, I had the pleasure of moderating a panel at a workshop titled “Post-Silicon Debug: Technologies, Methodologies, and Best-Practices.” This workshop brought together a collection of experts from industry, academia, and EDA to discuss the emerging challenges and solutions associated with post-silicon validation. The speakers presented different instrumentation … Read More
A system-level verification engineer once told me that his company consumes over 50% of its emulation capacity debugging failures. According to him there was just no way around consuming emulators while debugging their SoC design emulation runs. In fact when failures occur during emulation, verification engineers often turn to live debugging with JTAG interfaces to the Design Under Test. This enables … Read More
Functional Verification, Instant Replay, Emulation, Verification, Verification Academy, JTAG, SoC
Live & In-Person at DAC 2012!
Verification Academy, the brain child of Dr. Harry Foster, Chief Verification Scientist at Mentor Graphics, was live from the Design Automation Conference tradeshow floor this year. Harry is pictured to the right giving an update on his popular verification survey from the DAC tradeshow floor.
The Verification Academy, predominantly a web-based resource is a popular … Read More
Verification Academy, UVM Express, Tech Design Forum, ACE, AMS, Thales, UPF, UVM, ABV, Coverage Closure, iTBA, Low Power, DAC, OVM, ARM, Assertion-Based Verification, Formal, Doulos, Verification Trends
Open-Source Proof-of-Concept Library Released
Accellera Systems Initiative has released for general industry use an open-source proof-of-concept library as a companion to the recently minted IEEE Std. 1666™-2011, SystemC Language Reference Manual standard
In November 2011, the IEEE Standards Association approved IEEE Std. 1666-2011. The completed and published standard was made available to the community … Read More
UVM, Accellera Systems Initiative, 1666, SystemC, open-source, proof-of-concept library
Accellera Ushers in Unified Coverage Interoperability Standard (UCIS)
For the past few months, Accellera’s Unified Coverage Interoperability Standards working group has completed and released a new standard that is destined to help boost verification productivity and efficiency. Verification teams use a variety of verification technologies, many times from different suppliers, to achieve their verification … Read More
Hi Everyone,
Just wanted to make sure you’re aware of our next Recipe of the Month online Web Seminar: Scoreboards and Results Predictors in UVM on Thursday, July 12 at 9am PDT. You can register for the seminar here. This will be the ninth seminar in our ongoing Recipe of the Month seminar (see the full list here) and the reviews have been universally positive.
This particular seminar will outline … Read More
Graph-Based Intelligent Testbench Automation
While intelligent testbench automation is still reasonably new when measured in EDA years, this graph-based verification technology is being adopted by more and more verification teams every day. And the interest is global. Verification teams from Europe, North America, and the Pacific Rim are now using iTBA to help them verify their newest electronic … Read More
