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Verification Horizons Blog

9 Jul, 2014

Accellera Approves UVM 1.2

Posted by Dennis Brophy

Dennis Brophy Accellera has announced the completion of a multi-year effort to update its latest edition of the Universal Verification Methodology (UVM).  In completing this effort, the UVM 1.2 Class Reference Document was approved as an Accellera standard and the UVM Working Group has supplied an accompanying open-source reference implementation.  Questa supports UVM 1.2. In addition to the resources you can download … Read More

29 May, 2014

Matthew Ballance Verification engineers put lots of effort into writing and tuning constraints for random stimulus. It’s critical that the constraints correctly express the valid relationships between the stimulus variables. Otherwise, invalid stimulus will be generated or, worse, important valid combinations of stimulus will not be generated. When it comes to bug hunting, running open-loop random stimulus is recognized … Read More

21 May, 2014

Matthew Ballance If there was a tool that enabled you to create tests 10x more productively that you can today, would you change your entire verification language and testbench environment tomorrow? Not likely. Despite our love of technology that makes us more productive and efficient, lots of thought and planning goes into making big shifts in verification methodology. Now, what if that same 10x boost in test creation … Read More

7 May, 2014

The FPGA Verification Window Is Open

Posted by Joe Rodriguez

Joe Rodriguez My Feb. 4 post introduced Mentor Graphics’ three-step FPGA verification process intended to help design teams get out of the reprogrammable lab more effectively. Since then, I’ve engaged FPGA vendors, design managers and engineers to explain the process, paying special attention to the merits and technical detail for injecting automation into any FPGA verification environment, the hallmark of Mentor’s … Read More

Verilog, Verification, VHDL, Code Coverage, Coverage, Assertions, FPGA, Functional Verification

25 Apr, 2014

UVM DVCon 2014 Tutorial Video Online

Posted by Dennis Brophy

Dennis Brophy DVCon 2014 Conference Proceedings Published With record attendance announced for DVCon 2014, one might wonder if there is really a need to put some of the “Accellera Day” tutorial videos online.  With more than 1,000 professionals attending in some capacity, it would be easy to conclude that everyone that needs to know about UVM and the developments on the updated version to it, probably know.  Looking … Read More

DVCon, Functional Verification, Accellera, UVM, register layer, stimulus generation

10 Apr, 2014

Dennis Brophy Its always fun to take the wraps off of solutions we have been hard at work developing.  The global team of Mentor Graphics engineers have spent considerable time and energy to bring the next level of SoC design and verification productivity to what seems to be a never ending response to Moore’s Law.  As silicon feature sizes get smaller, design sizes get larger and the verification problem mushrooms.  … Read More

UPF, UVM, Codelink, Enterprise Verification Platform, Accellera, Portable Stimulus, Gary Smith EDA, Moore's Law

17 Mar, 2014

New Verification Academy ABV Course

Posted by Harry Foster

Harry Foster As some of you might be aware, the Verification Academy has a video course dedicated to the topic of Assertion-Based Verification (ABV). In fact, this was the first video course we released for the academy almost six years ago. To date, it has remained one of our most popular courses. Yet one of the most common requests for improvement to this course has been adding content that focuses more on the … Read More

3 Mar, 2014

Tom Fitzpatrick DVCon is always one of my favorite events in our industry, and I am proud to let you know that the latest issue of Verification Horizons is available “hot off the presses” at the Verification Academy to mark the occasion. For those of you attending the conference, please consider this issue as an addendum to the great technical program being offered (especially paper 8.1, “Of Camels and Committees: … Read More

UVM, Verification Academy, DVCon, Verification Horizons

27 Feb, 2014

DVCon–The FREE Side

Posted by Dennis Brophy

Dennis Brophy Psst!  I’ll let you in on some news… While DVCon calls the free portion of the conference “Exhibits Only,” let me share a little secret for you – You also gain access to the conference panels and the keynote presentation. For those in Silicon Valley and local to DVCon, I invite you to register for the FREE side of the conference, not just for the conference exhibition that will have (in evening hours) … Read More

Software, Verification, DVCon, Verification Gap

25 Feb, 2014

More DVCon–More Mentor Tutorials!

Posted by Dennis Brophy

Dennis Brophy As DVCon expands, we at Mentor Graphics have grown our sponsored sessions as well.  Would you expect less? In DVCon’s recent past, it was a tradition for the North American SystemC User Group (NASCUG) to sponsor a day of activity before the official start of the conference.  When OSCI merged with Accellera, the day before the official conference start grew to become Accellera Day with a broader set … Read More

DVCon, Emulation, Accellera, SystemC, Formal Verification, fpga prototype

23 Feb, 2014

UVM 1.2: Open Public Review

Posted by Dennis Brophy

Dennis Brophy UVM 1.2 Release is Imminent As vice chair of DVCon 2014, I can share with you that the Universal Verification Methodology (UVM) remains a topic of great interest.  It sets the pace for tutorials and given the pending release by Accellera, learning what is new in UVM 1.2 is a compelling reason to attend DVCon. The Accellera Day tutorial series on Monday at DVCon is popular with UVM being a session of … Read More

DVClub, DVCon, Accellera, Universal Verification Methodology, UVM 1.2, Git, OSCI

11 Feb, 2014

DVCon 2014: Standards on Display

Posted by Dennis Brophy

Dennis Brophy One of the nice things about DVCon is the update one can get from the developers of IEEE and Accellera standards.  And this year’s DVCon is no exception.  The four days of DVCon begin and end with tutorials that cover updates to popular standards like UVM, UPF, SystemC and more.  For our part, Mentor Graphics is participating in the development and delivery of these updates with our peers. I have written … Read More

IEEE 1801, DVCon, UVM, SystemC, UPF

4 Feb, 2014

Joe Rodriguez Marketing teams at FPGA vendors have been busy as the silicon nanometer geometry race escalates. Altera is “delivering the unimaginable” while Xilinx is offering “all programmable SoCs” to design centers. It’s clear that the SoC has become more accessible to a broader market today and that FPGA vendors have staked out a solid technology roadmap for the near future. Do marketing … Read More

Verilog, Verification, VHDL, Code Coverage, Coverage, Assertions, FPGA, Functional Verification

6 Jan, 2014

Dennis Brophy The UCIS Story There is no secret as design sizes grow it is doubly burdensome for verification.  Two factors that are easy to measure is the time it takes to simulate a design and the other is the size of the dataset that contains the results of the verification runs. Simulation times are growing and the datasets are getting larger.  While time and attention is given to accelerated verification through … Read More

Coverage Closure, DVClub, Accellera, UCIS, Unified Coverage Interoperability Standard, Metrics

28 Nov, 2013

Harry Foster Wow! I’ve been on the road since August, and finally found a spare moment to get back to this blog. I started this blog series with a prologue that gave a little bit of background on the 2012 Wilson Research Group study. And with this epilogue, I will draw the series to a conclusion with some insight on the study process. Many people believe that industry studies in general (and particularly ones … Read More

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