Posted Dec 13, 2011, by Mark Olen
Instant Replay Offers Multiple Views at Any Speed
If you’ve watched any professional sporting event on television lately, you’ve seen the pressure put on referees and umpires. They have to make split-second decisions in real-time, having viewed ultra-high-speed action just a single time. But watching at home on television, we get the luxury of viewing multiple replays of events in question … Read More
Tags:
Verification,
testbench,
Software as a Testbench,
SoC,
Functional Verification,
Cortex,
SoC Level Verification,
ARM
Posted Dec 5, 2011, by Dennis Brophy
The DASC Participates in IEEE Standards Association Gala Event
The IEEE Computer Society Design Automation Standards Committee (DASC) participated in the annual IEEE Standards Association (SA) Award ceremony held in New Brunswick, NJ USA on 4 December 2011. Hundreds met to recognize the work of thousands who volunteer daily to develop standards and to honor the few who are exceptional examples.
The … Read More
Posted Nov 22, 2011, by Dave Rich
The word override is heavily overloaded in object oriented programming. This concept can make object-oriented programming very difficult to understand. Ironically, the very concept of object-oriented programming came from a simulation language called “Simula” in the 1960′s. Both Verilog and C++ are descendants of this language, but took different paths along the way to represent objects.
In … Read More
Posted Nov 11, 2011, by Dave Rich
Adopting SystemVerilog can be challenging to some, and learning the UVM at the same time might seem overwhelming. There is no getting over the fact that if you are going to develop any reasonably sized testbench in SystemVerilog, you need to learn how to declare and construct a class. You also need to learn a few Object-Oriented programming principals so you can extend a UVM class into something for … Read More
Tags:
UVM,
Verification Methodology
Posted Nov 10, 2011, by Dennis Brophy
IEEE Announces Revision to IEEE 1666™ – Adds Transaction-Level Modeling Support
A significant step forward to address standards for advanced system-on-chip (SoC) designs has taken place by the IEEE. The IEEE announced the new revision of the SystemC standard, known as IEEE 1666™-2011, has been approved. While it is a revision of the current SystemC standard, IEEE 1666™-2005, the major new feature … Read More
Tags:
SystemC,
TLM,
Accellera,
1666,
OVM,
TLM 1.0,
TLM 2.0,
UVM,
OSCI,
Verification Academy
Posted Oct 31, 2011, by Russ Klein
For Halloween this year I’ll be blogging a real horror story. And when I say “real”, I mean real – everything you are about to read is the truth. Not some Spielberg made up scary stuff. Knowing that it’s real makes it just a bit scarier. I’ve obfuscated some details to protect the identity of both the innocent and the guilty.
It all started some months ago, I was getting off a train in a European … Read More
Posted Oct 13, 2011, by Dennis Brophy
Creating Confidence Globally
Today, 14 October 2011, is the day the world celebrates standards. The leadership of the IEC, ISO and ITU issued a message in support of it that clearly articulates the role standards play in safety, reliability, interoperability, their impact on business efficiency and more.
And from time-to-time, I have had the opportunity to join the celebration the American National … Read More
Posted Oct 13, 2011, by Dennis Brophy
Legacy’s Luster Lost
As a follow-on to my last blog, where I shared information about Harry Foster speaking live about the research he has been reporting on the last year and where I noted legacy might hold some back, I was going to finish on some of the work we have done at Mentor Graphics to move forward while trying to keep some of those held back by legacy, whole.
Buy why this title? For some, … Read More
Tags:
VHS,
Verification,
VIP-TSC,
betamax,
e,
Accellera,
UVM,
OVM
Posted Oct 5, 2011, by Dennis Brophy
Is Legacy Holding You Back?
Harry Foster, Mentor’s Verification Chief Scientist, will take center stage to give live presentations on the pressing SoC verification issues as he highlights recent research he has been reporting on in his numerous blogs. The first event will be held in San Jose, CA USA (18 October 2011) and the second event will be held in Reading, UK (15 November 2011).
Harry has been … Read More
Tags:
VMM,
VIP-TSC,
Accellera,
UVM,
OVM
Posted Sep 13, 2011, by Tom Fitzpatrick
I’m excited to announce that our second UVM Recipe-of-the-Month Webinar, “Sequence Layering,” will be presented on Thursday, September 15, at 1pm EDT(/10am PDT). To join over 240 of your colleagues and/or competitors in viewing this webinar, please see here. The webinar should take about an hour. If you can’t make it for the live viewing, the webinar will be archived for later … Read More
