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Verification Horizons Blog

11 Feb, 2014

DVCon 2014: Standards on Display

Posted by Dennis Brophy

Dennis Brophy One of the nice things about DVCon is the update one can get from the developers of IEEE and Accellera standards.  And this year’s DVCon is no exception.  The four days of DVCon begin and end with tutorials that cover updates to popular standards like UVM, UPF, SystemC and more.  For our part, Mentor Graphics is participating in the development and delivery of these updates with our peers. I have written … Read More

IEEE 1801, DVCon, UVM, SystemC, UPF

4 Feb, 2014

Joe Rodriguez Marketing teams at FPGA vendors have been busy as the silicon nanometer geometry race escalates. Altera is “delivering the unimaginable” while Xilinx is offering “all programmable SoCs” to design centers. It’s clear that the SoC has become more accessible to a broader market today and that FPGA vendors have staked out a solid technology roadmap for the near future. Do marketing … Read More

Verilog, Verification, VHDL, Code Coverage, Coverage, Assertions, FPGA, Functional Verification

6 Jan, 2014

Dennis Brophy The UCIS Story There is no secret as design sizes grow it is doubly burdensome for verification.  Two factors that are easy to measure is the time it takes to simulate a design and the other is the size of the dataset that contains the results of the verification runs. Simulation times are growing and the datasets are getting larger.  While time and attention is given to accelerated verification through … Read More

Coverage Closure, DVClub, Accellera, UCIS, Unified Coverage Interoperability Standard, Metrics

28 Nov, 2013

Harry Foster Wow! I’ve been on the road since August, and finally found a spare moment to get back to this blog. I started this blog series with a prologue that gave a little bit of background on the 2012 Wilson Research Group study. And with this epilogue, I will draw the series to a conclusion with some insight on the study process. Many people believe that industry studies in general (and particularly ones … Read More

15 Nov, 2013

New Verification Horizons Issue Available

Posted by Tom Fitzpatrick

Tom Fitzpatrick Wanted to let you all know that the October, 2013 issue of Verification Horizons is available online. You can view the articles or download the issue here. In addition to a little paternal bragging in the Introduction, I wanted to call your attention in particular to a few of the articles written by some Mentor colleagues: Software-Driven Testing of AXI Bus in a Dual Core ARM System by Mark Olen, Mentor … Read More

30 Oct, 2013

Mark Olen MENTOR GRAPHICS AT ARM TECHCON This week ARM® TechCon® 2013 is being held at the Santa Clara Convention Center from Tuesday October 29 through Thursday October 31st, but don’t worry, there’s nothing to be scared about.  The theme is “Where Intelligence Counts”, and in fact as a platinum sponsor of the event, Mentor Graphics is excited to present no less than ten technical and training sessions about … Read More

testbench, SoC, Verification, Formal Verification, functional coverage, ARM, Verification Academy, iTBA, Functional Verification, Intelligent Testbench Automation

15 Oct, 2013

Dennis Brophy Low Power Flow Kicks-off Symposium In the world of electronic design automation, as an idea takes hold and works its way from thought to silicon, numerous tools are used by engineers and the like to help bring a good idea to product fruition.  Standards play a key and important role to help move your user information from high-level concepts into the netlists can be realized in silicon.  The IEEE Standards … Read More

UPF, IEEE 1801, ieee standards association, ARM, Questa Vanguard Partnership, Interoperability, Low Power

4 Oct, 2013

Harry Foster We are truly living in the age of SoC design, where 78 percent of all designs today contain one or more embedded processors.  In fact, 56 percent of all designs contain two or more embedded processors, which brings a whole new level of verification challenges—requiring unique solutions. A great example of this is STMicroelectronics who recently shared their experience and solution in addressing verification … Read More

OVM, Emulation, UVM, SystemC

19 Sep, 2013

Dave Rich It’s hard for me to believe that SystemVerilog 3.1 was released just over 10 years ago. The 3.1 version added Object-Oriented Programming features for testbench development to a language predominately used for RTL design synthesis. Making debug easier was one of the driving forces in unifying testbench and design features into a single language. The semantics for evaluating expressions and executing … Read More

Accellera, testbench, Verification

8 Sep, 2013

Harry Foster Schedules, respins, and bug classification This blog is a continuation of a series of blogs that present the highlights from the 2012 Wilson Research Group Functional Verification Study (for a background on the study, click here). In my previous blog (Part 11 click here), I focused on some of the 2012 Wilson Research Group findings related to formal verification, acceleration/emulation, and FPGA prototyping … Read More

IEEE 1800, Accellera

26 Aug, 2013

Harry Foster Verification Techniques & Technologies Adoption Trends This blog is a continuation of a series of blogs that present the highlights from the 2012 Wilson Research Group Functional Verification Study (for background on the study, click here). In my previous blog (Part 9 click here), I focused on some of the 2012 Wilson Research Group findings related to design and verification language and library … Read More

testbench, UVM, Assertion-Based Verification, Coverage, Accellera, Verification Academy, functional coverage, Functional Verification

19 Aug, 2013

Harry Foster Verification Techniques & Technologies Adoption Trends This blog is a continuation of a series of blogs that present the highlights from the 2012 Wilson Research Group Functional Verification Study (for background on the study, click here). In my previous blog (Part 9 click here), I focused on some of the 2012 Wilson Research Group findings related to design and verification language and library … Read More

testbench, UVM, Assertion-Based Verification, Coverage, Accellera, Verification Academy, functional coverage, Functional Verification

12 Aug, 2013

Harry Foster Language and Library Trends (Continued) This blog is a continuation of a series of blogs that present the highlights from the 2012 Wilson Research Group Functional Verification Study (for a background on the study, click here). In my previous blog (Part 8 click here), I focused on design and verification language trends, as identified by the Wilson Research Group study. This blog presents additional … Read More

SVA, UVM, Accellera, Assertion-Based Verification, Verification Methodology, OVL, PSL, Functional Verification

5 Aug, 2013

Harry Foster Language and Library Trends This blog is a continuation of a series of blogs that present the highlights from the 2012 Wilson Research Group Functional Verification Study (for a background on the study, click here). In my previous blog (Part 7 click here), I focused on some of the 2012 Wilson Research Group findings related to testbench characteristics and simulation strategies. In this blog, I present … Read More

IEEE 1800, RTL, VHDL, 1364, testbench, Verification, Verification Academy, 1076, Verilog, Functional Verification, SystemC, Accellera, functional coverage

29 Jul, 2013

Harry Foster Testbench Characteristics and Simulation Strategies This blog is a continuation of a series of blogs that present the highlights from the 2012 Wilson Research Group Functional Verification Study (for background on the study, click here). In my previous blog (click here), I focused on the controversial topic of effort spent in verification. In this blog, I focus on some of the 2012 Wilson Research Group … Read More

testbench, UVM, Accellera, Formal Verification, Verification, IEEE 1800, Functional Verification

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