Advanced verification techniques including functional coverage and constrained random stimulus generation have proven themselves invaluable in the design of the smallest FPGAs to the largest SoCs today. Still many design and verification teams that need to and are willing to embrace these technologies have yet to do so. Verification environments written with basic hardware description languages like … Read More
In his recent post on UVM: Some Thoughts Before DVCon, Dennis outlined some great ideas about what we think should happen next for UVM. His 3rd point, “UVM needs to bridge the system domain,” is particularly relevant given the newly-formed Accellera Systems Initiative. This is actually an area we’ve been contemplating for a while here at Mentor, and as Dennis indicated, we shared our thoughts on this … Read More
Verification Methodology, Verification Academy, Functional Verification, SystemC, DVCon, UVM Connect, UVM-1.1, UVM
Is my car trying to tell me something?
This past Friday was the beginning of a two day internal functional verification meeting at Mentor Graphics corporate headquarters on Intelligent Testbench Automation (iTBA). (Mentor’s iTBA product, Questa inFact is hot and getting hotter.) After getting to my car to return home at the end of the first day, I was thinking that the large interest in this technology … Read More
UVM, Tipping Point, Veloce, inFact, Intelligent Testbench Automation, Crossing the Chasam, Questa, SoC, iTBA, OVM
It is time to talk about what happens next with UVM
The Design and Verification Conference (DVCon) has become the premier event to discuss front-end design issues with an emphasis on verification. If one listens to the Conversation Central interview of DVCon leadership it is clear how singularly important DVCon is. As one of the three organizers of the UVM Tutorial on Monday, I know the conference … Read More
“Ready, Set, Deploy”
The last half year has seen a theme from Accellera Systems Initiative that declares its Universal Verification Methodology (UVM) is ready for design and verification teams to adopt. This theme started with a whitepaper from Accellera I authored with two of my peers, Stan Krolikoski from Cadence Design Systems and Yatin Trivedi from Synopsys. A day long UVM tutorial will be featured … Read More
IEEE Std. 1666™-2011 Available as Free Download
In November 2011 I blogged the IEEE Standards Association (SA) approved a revision to the popular SystemC standard, known officially as IEEE Std. 1666™-2011. One of the key elements of this standard includes the addition of Transaction Level Modeling (TLM). I pointed to several online resources to learn more about the revised SystemC standard in that … Read More
I think very few engineers would argue with the claim that the longer a bug goes undetected, the more expensive it is to fix. In fact, the general rule-of-thumb is that the cost to fix a bug increases by an order of magnitude as a project progresses from one milestone to the next. Bugs found before simulation obviously have the lowest cost. Bugs found at block or subsystem simulation are generally easier … Read More
Instant Replay Offers Multiple Views at Any Speed
If you’ve watched any professional sporting event on television lately, you’ve seen the pressure put on referees and umpires. They have to make split-second decisions in real-time, having viewed ultra-high-speed action just a single time. But watching at home on television, we get the luxury of viewing multiple replays of events in question … Read More
Verification, testbench, SoC Level Verification, Cortex, ARM, Software as a Testbench, Functional Verification, SoC
The DASC Participates in IEEE Standards Association Gala Event
The IEEE Computer Society Design Automation Standards Committee (DASC) participated in the annual IEEE Standards Association (SA) Award ceremony held in New Brunswick, NJ USA on 4 December 2011. Hundreds met to recognize the work of thousands who volunteer daily to develop standards and to honor the few who are exceptional examples.
The … Read More
The word override is heavily overloaded in object oriented programming. This concept can make object-oriented programming very difficult to understand. Ironically, the very concept of object-oriented programming came from a simulation language called “Simula” in the 1960′s. Both Verilog and C++ are descendants of this language, but took different paths along the way to represent objects.
In … Read More
Adopting SystemVerilog can be challenging to some, and learning the UVM at the same time might seem overwhelming. There is no getting over the fact that if you are going to develop any reasonably sized testbench in SystemVerilog, you need to learn how to declare and construct a class. You also need to learn a few Object-Oriented programming principals so you can extend a UVM class into something for … Read More
IEEE Announces Revision to IEEE 1666™ – Adds Transaction-Level Modeling Support
A significant step forward to address standards for advanced system-on-chip (SoC) designs has taken place by the IEEE. The IEEE announced the new revision of the SystemC standard, known as IEEE 1666™-2011, has been approved. While it is a revision of the current SystemC standard, IEEE 1666™-2005, the major new feature … Read More
SystemC, TLM, Accellera, 1666, OVM, TLM 1.0, TLM 2.0, UVM, OSCI, Verification Academy
For Halloween this year I’ll be blogging a real horror story. And when I say “real”, I mean real – everything you are about to read is the truth. Not some Spielberg made up scary stuff. Knowing that it’s real makes it just a bit scarier. I’ve obfuscated some details to protect the identity of both the innocent and the guilty.
It all started some months ago, I was getting off a train in a European … Read More
Creating Confidence Globally
Today, 14 October 2011, is the day the world celebrates standards. The leadership of the IEC, ISO and ITU issued a message in support of it that clearly articulates the role standards play in safety, reliability, interoperability, their impact on business efficiency and more.
And from time-to-time, I have had the opportunity to join the celebration the American National … Read More
Legacy’s Luster Lost
As a follow-on to my last blog, where I shared information about Harry Foster speaking live about the research he has been reporting on the last year and where I noted legacy might hold some back, I was going to finish on some of the work we have done at Mentor Graphics to move forward while trying to keep some of those held back by legacy, whole.
Buy why this title? For some, … Read More
