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Verification Horizons Blog

22 Jul, 2013

Harry Foster Effort Spent On Verification (Continued) This blog is a continuation of a series of blogs that present the highlights from the 2010 Wilson Research Group Functional Verification Study (for a background on the study, click here). In my previous blog (click here), I focused on the controversial topic of effort spent in verification. This blog continues that discussion. I stated in my previous blog that … Read More

Verification Academy, Verification, Verification Methodology, Formal Verification, Functional Verification, Accellera, UVM, IEEE 1800

16 Jul, 2013

Dave Rich It is often said that the English language is one of the most difficult languages to learn: inconsistent spelling rules; the same words are used with different meanings in different contexts. “Why does a farmer produce produce? Working on the SystemVerilog IEEE 1800 standard, I understand that even more clearly now. The word class is used many times in different contexts to mean slightly different … Read More

15 Jul, 2013

Harry Foster   Effort Spent in Verification This blog is a continuation of a series of blogs that present the highlights from the 2012 Wilson Research Group Functional Verification Study (click here). In my previous blog (click here), I focused on design and verification reuse trends. In this blog, I focus on the controversial topic of the amount of effort spent in verification. Directly asking study participants … Read More

Functional Verification, Accellera, Verification Academy, Verification Methodology, Verification

8 Jul, 2013

Harry Foster Reuse Trends This blog is a continuation of a series of blogs that present the highlights from the 2012 Wilson Research Group Functional Verification Study (click here).  In my previous blog (click here), I focused on clocking and power management.  In this blog, I focus on design and verification reuse trends. As I mentioned in my prologue blog to this series (click here), one interesting trend that … Read More

Functional Verification, Reuse, Formal Verification, Verification Academy, Verification Methodology

28 Jun, 2013

Harry Foster Clocking and Power Trends In Part 2 of this series of blogs, I continued the discussion focused on design trends (click here) as identified by the 2012 Wilson Research Group Functional Verification Study (click here). In this blog, I continue presenting the study findings related to design trends, with a focus on clocking and power trends. Independent Asynchronous Clock Domains Figure 1 shows the percentage … Read More

Verification Academy, Verification, Verification Methodology, Functional Verification, Accellera, Wilson Research Group Study, UPF, IEEE 1801, Low Power

26 Jun, 2013

Harry Foster Design Trends (Continued) In Part 1 of this series of blogs, I focused on design trends (click here) as identified by the 2012 Wilson Research Group Functional Verification Study (click here). In this blog, I continue presenting the study findings related to design trends, with a focus on embedded processor, DSP, and on-chip bussing trends. Embedded Processors In Figure 1, we see the percentage of today’s … Read More

31 May, 2013

Tom Fitzpatrick Hi Everyone, Just wanted to let you know that we just posted the PDF of the latest, Texas-Sized, DAC edition of Verification Horizons on the Verification Academy. In addition to my Editor’s Note, in which I liken what we do as verification engineers to my set-building experiences in local theatre groups, and brag about my daughter, you’ll find these fine articles: Interviewing a Verification Engineer  … Read More

Verification Academy, DAC

29 May, 2013

Dennis Brophy Download the standard now – at no charge The IEEE Standards Association (IEEE-SA) has published the latest UPF 2.1 standard, officially called IEEE Standard for Design and Verification of Low-Power Integrated Circuits, many refer to it as IEEE 1801 or UPF for the Unified Power Format as this was the name Accellera had given it prior to transferring standardization responsibility and ongoing maintenance … Read More

UPF, DAC, IEEE 1801, Accellera, Low Power, IEEE Get, ieee standards association

8 May, 2013

Harry Foster  Design Trends In my previous blog, I introduced the 2012 Wilson Research Group Functional Verification Study (click here). The objective of my previous blog was to provide background on this large, worldwide industry study. I will present the key findings from this study in a set of upcoming blogs.  This blog begins the process of revealing the 2012 Wilson Research Group study findings by first focusing … Read More

Functional Verification, Accellera, Verification Academy, IEEE 1800, Verification

3 May, 2013

Dave Rich A unique concept most beginners have trouble grasping about the Verilog, and now the SystemVerilog, Hardware Description Language (HDL) is the difference between wire’s (networks) and reg‘s (variables). This concept is something that every experienced RTL designer should be familiar with, but there are now many verification engineers with no prior Verilog experience trying to pick up SystemVerilog … Read More

Verification, Functional Verification, Verilog

29 Apr, 2013

Dennis Brophy Power Aware Verification Course Modules Released I guess I could continue the puns on the low-power theme as a few readers may get a charge out of it.  And there is a reason I seem to gravitate to puns from the start.  The first chair of the IEEE 1801 committee and I exchanged puns one time that resulted in him shipping me a Pun DVD that recorded a pun contest in which one person and another tried to … Read More

Low Power, Power Aware Verification, IEEE 1801, UPF

23 Apr, 2013

Harry Foster This is the first in a series of blogs that presents the results from the 2012 Wilson Research Group Functional Verification Study. Study Overview In 2002 and 2004, Ron Collett International, Inc. conducted its well known ASIC/IC functional verification studies, which provided invaluable insight into the state of the electronic industry and its trends in design and verification. However, after the 2004 … Read More

UVM, Assertion-Based Verification, Formal Verification, Accellera, Verification Academy, Verification Methodology, functional coverage, Verilog, Functional Verification, VHDL

19 Mar, 2013

Even More UVM Debug in Questa 10.2

Posted by Tom Fitzpatrick

Tom Fitzpatrick We’re really excited about the recent Questa 10.2 release, and I’m sure you’ll be just as excited when you check it out. For you UVM-philes out there, we’ve extended our industry-leading UVM Debug features to make your life even easier. I’ll present a quick overview of the new features here, but you’ll really want to get your hands on 10.2 and take a more in-depth … Read More

UVM, Questa

14 Mar, 2013

IEEE Approves New Low Power Standard

Posted by Dennis Brophy

Dennis Brophy IEEE 1801™-2013 Enters Pre-Publish Phase The completion and approval of electronic design automation standards has seemed to be the order of the day for several months now.  Added to this list is the IEEE Standards Association (SA) approval of their newly revised low power standard (IEEE 1801™-2013).  The IEEE SA’s Review Committee (RevCom) unanimously recommended approval and that was confirmed by … Read More

UPF, Erich Marschner, IEEE 1801, DVCon, RevCom, Low Power

27 Feb, 2013

Tom Fitzpatrick Hi Everyone, Just wanted to let you all know that the new issue of Verification Horizons is now available. If you’re at DVCon this week, you can get a printed copy (and maybe get an author or two to sign it) at various places around the conference, especially at our tutorial on Thursday morning. If you’re not at the conference, you can get it online at the Verification Academy. Please be … Read More

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