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24 Oct, 2012

Tom Fitzpatrick Hi Everyone, Just wanted to let you know that the latest and greatest edition of Verification Horizons is now available. The articles in this issue all discuss how you can apply new techniques and technology to achieve greater verification productivity. And for you football (I mean “American football” as opposed to “soccer”) fans out there, be sure and check out the Editor’s … Read More

18 Oct, 2012

Harry Foster

When it comes to formal methods, many engineers are skeptics. Perhaps this is due to value propositions that have been pitched over the years that have over-promised yet under-delivered in terms of results. Or perhaps it is due to the advanced skills that have traditionally been required to achieve predictable and reliable results. After all, historically this was the case—dating back to the mid-nineties

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16 Oct, 2012

Dennis Brophy A new style takes center stage It was Fashion Week in Portland, Oregon in early October.  And while the thought of Portland and fashion might not be believable to many in the world, especially those who look to the design houses of Paris or Milan, it was.  What struck me was the blend of fashion with high tech this year.  Intel took the opportunity to roll out its fashion inspired campaign (dressing … Read More

UVM, UVM Cookbook, OVM, Verification, Verification Academy

10 Sep, 2012

OVM Gets Connected

Posted by Dennis Brophy

Dennis Brophy

OVM Bridges SystemVerilog and SystemC Languages When UVM Connect was first released, the multilingual connection between IEEE Std. 1800™ (SystemVerilog) and IEEE Std. 1666™ (SystemC) standards bridged the two languages to allow design and verification engineers to access UVM from SystemC or SystemVerilog to exploit native languages advantages.  OVM users wondered if it was possible to support them as

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Multilanguage OVM, Multilanguage UVM, SystemC

28 Aug, 2012

Open Stand & EDA Standardization

Posted by Dennis Brophy

Dennis Brophy Five Leading Global Organizations Affirm “The Modern Paradigm for Standards” The EDA industry has seen changes to the international standards paradigm the past few decades.   When industry helped launch VHDL with the help of government support, it transferred ongoing maintenance and enhancement to the IEEE when it completed its first version.  In addition to anchoring the standard at the IEEE, … Read More

VHDL, IAB, iec, Accellera, W3C, ITEF, Open Stand, Internet Society

27 Jul, 2012

Harry Foster At the 2012 Design Automation Conference, I had the pleasure of moderating a panel at a workshop titled “Post-Silicon Debug: Technologies, Methodologies, and Best-Practices.” This workshop brought together a collection of experts from industry, academia, and EDA to discuss the emerging challenges and solutions associated with post-silicon validation. The speakers presented different instrumentation … Read More


26 Jul, 2012

Virtual Emulation for Debugging

Posted by Mark Olen

Mark Olen A system-level verification engineer once told me that his company consumes over 50% of its emulation capacity debugging failures. According to him there was just no way around consuming emulators while debugging their SoC design emulation runs. In fact when failures occur during emulation, verification engineers often turn to live debugging with JTAG interfaces to the Design Under Test. This enables … Read More

Functional Verification, Instant Replay, Emulation, Verification, Verification Academy, JTAG, SoC

20 Jul, 2012

Dennis Brophy Live & In-Person at DAC 2012! Verification Academy, the brain child of Dr. Harry Foster, Chief Verification Scientist at Mentor Graphics, was live from the Design Automation Conference tradeshow floor this year.  Harry is pictured to the right giving an update on his popular verification survey from the DAC tradeshow floor. The Verification Academy, predominantly a web-based resource is a popular … Read More

Formal, Doulos, Verification Academy, UVM Express, Verification Trends, Tech Design Forum, ACE, Thales, AMS, UPF, ABV, UVM, Coverage Closure, iTBA, DAC, Low Power, ARM, OVM, Assertion-Based Verification

16 Jul, 2012

SystemC Standardization Cycle Completes

Posted by Dennis Brophy

Dennis Brophy Open-Source Proof-of-Concept Library Released Accellera Systems Initiative has released for general industry use an open-source proof-of-concept library as a companion to the recently minted IEEE Std. 1666™-2011, SystemC Language Reference Manual standard In November 2011, the IEEE Standards Association approved IEEE Std. 1666-2011.  The completed and published standard was made available to the community … Read More

UVM, Accellera Systems Initiative, 1666, SystemC, open-source, proof-of-concept library

12 Jul, 2012

Dennis Brophy Accellera Ushers in Unified Coverage Interoperability Standard (UCIS) For the past few months, Accellera’s Unified Coverage Interoperability Standards working group has completed and released a new standard that is destined to help boost verification productivity and efficiency.  Verification teams use a variety of verification technologies, many times from different suppliers, to achieve their verification … Read More

DAC, DVCon, Accellera, UCIS, UCDB

9 Jul, 2012

Tom Fitzpatrick Hi Everyone, Just wanted to make sure you’re aware of our next Recipe of the Month online Web Seminar: Scoreboards and Results Predictors in UVM on Thursday, July 12 at 9am PDT. You can register for the seminar here. This will be the ninth seminar in our ongoing Recipe of the Month seminar (see the full list here) and the reviews have been universally positive. This particular seminar will outline … Read More

28 Jun, 2012

Mark Olen

Graph-Based Intelligent Testbench Automation While intelligent testbench automation is still reasonably new when measured in EDA years, this graph-based verification technology is being adopted by more and more verification teams every day.  And the interest is global.  Verification teams from Europe, North America, and the Pacific Rim are now using iTBA to help them verify their newest electronic designs

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31 May, 2012

Two Articles You Need to Check Out

Posted by Tom Fitzpatrick

Tom Fitzpatrick As Editor of Verification Horizons, I’d like to point out a couple of articles that you really need to check out, if you haven’t already. If you want to take a look at full issues of Horizons, you can find them here. I’m sure many of you have found yourselves in the painful situation of trying to track down a hard-to-reach coverage hole only to find out, after way too much time, that … Read More

30 May, 2012

Off to DAC!

Posted by Dennis Brophy

Dennis Brophy Where might our paths cross? It is always challenge to fit all the needed visits in during the Design Automation Conference (DAC).  If you happen to like some of the same events I attend, then the chances are good our paths might cross in public. Saturday and Sunday are busy with an Accellera Systems Initiative board meeting.  Split across two days, Accellera board members will meet to conduct traditional … Read More

UPF, UCIS, UVM, DAC, EDAC, Accellera, Verification Academy, SystemC, TLM, Gary Smith

12 May, 2012

Dave Rich Featured on EEWeb

Posted by Tom Fitzpatrick

Tom Fitzpatrick I’m sure many of you know my colleague, Dave Rich. I’ve known Dave since our days at Co-Design Automation when we worked together defining the Superlog language, which eventually became SystemVerilog after being donated to Accellera. Hard to believe that was 11 years ago. Having gotten to know Dave as a friend as well as a colleague over that time, I really enjoyed learning even more about him in his … Read More



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