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Download the standard now – at no charge The IEEE Standards Association (IEEE-SA) has published the latest UPF 2.1 standard, officially called IEEE Standard for Design and Verification of Low-Power Integrated Circuits, many refer to it as IEEE 1801 or UPF for the Unified Power Format as this was the name Accellera had given it prior to transferring standardization responsibility and ongoing maintenance … Read More

UPF, DAC, IEEE 1801, Accellera, Low Power, IEEE Get, ieee standards association

 Design Trends In my previous blog, I introduced the 2012 Wilson Research Group Functional Verification Study (click here). The objective of my previous blog was to provide background on this large, worldwide industry study. I will present the key findings from this study in a set of upcoming blogs.  This blog begins the process of revealing the 2012 Wilson Research Group study findings by first focusing … Read More

Functional Verification, Accellera, Verification Academy, IEEE 1800, Verification

This is the first in a series of blogs that presents the results from the 2012 Wilson Research Group Functional Verification Study. Study Overview In 2002 and 2004, Ron Collett International, Inc. conducted its well known ASIC/IC functional verification studies, which provided invaluable insight into the state of the electronic industry and its trends in design and verification. However, after the … Read More

UVM, Assertion-Based Verification, Formal Verification, Accellera, Verification Academy, Verification Methodology, functional coverage, Verilog, Functional Verification, VHDL

Today at this week’s DVCon 2013 conference, the IEEE Standards Association (IEEE-SA) and Accellera Systems Initiative (Accellera) have jointly announced the public availability of the IEEE 1800 SystemVerilog Language Reference Manual at no charge through the IEEE Get Program. As I posted a few weeks ago, the 1800-2012 is not a major revision of the standard, but does contain a few enhancements … Read More

Functional Verification, Accellera

Verification Academy Adds Major New Technical Resource The Verification Academy adds another major methodology cookbook to focus on effective coverage adoption.  The Coverage Cookbook describes the different types of coverage that are available to track your verification process progress, how to create a functional coverage model from a specification, and provides examples to implement functional … Read More

OVM, UCDB, Coverage, Coverage Closure, Accellera, UCIS, Harry Foster, UVM, IEEE 1800, Coverage Cookbook, Verification Academy, functional coverage

Accellera Ushers in Unified Coverage Interoperability Standard (UCIS) For the past few months, Accellera’s Unified Coverage Interoperability Standards working group has completed and released a new standard that is destined to help boost verification productivity and efficiency.  Verification teams use a variety of verification technologies, many times from different suppliers, to achieve their verification … Read More

DAC, DVCon, Accellera, UCIS, UCDB

Where might our paths cross? It is always challenge to fit all the needed visits in during the Design Automation Conference (DAC).  If you happen to like some of the same events I attend, then the chances are good our paths might cross in public. Saturday and Sunday are busy with an Accellera Systems Initiative board meeting.  Split across two days, Accellera board members will meet to conduct traditional … Read More

UPF, UCIS, UVM, DAC, EDAC, Accellera, Verification Academy, SystemC, TLM, Gary Smith

It is time to talk about what happens next with UVM The Design and Verification Conference (DVCon) has become the premier event to discuss front-end design issues with an emphasis on verification.  If one listens to the Conversation Central interview of DVCon leadership it is clear how singularly important DVCon is.  As one of the three organizers of the UVM Tutorial on Monday, I know the conference … Read More

DATE Conference, DVCon, Accellera, UVM, SystemC

IEEE Announces Revision to IEEE 1666™ – Adds Transaction-Level Modeling Support A significant step forward to address standards for advanced system-on-chip (SoC) designs has taken place by the IEEE.  The IEEE announced the new revision of the SystemC standard, known as IEEE 1666™-2011, has been approved.  While it is a revision of the current SystemC standard, IEEE 1666™-2005, the major new feature … Read More

SystemC, TLM, Accellera, 1666, OVM, TLM 1.0, TLM 2.0, UVM, OSCI, Verification Academy

Legacy’s Luster Lost As a follow-on to my last blog, where I shared information about Harry Foster speaking live about the research he has been reporting on the last year and where I noted legacy might hold some back, I was going to finish on some of the work we have done at Mentor Graphics to move forward while trying to keep some of those held back by legacy, whole. Buy why this title?  For some, … Read More

VHS, Verification, VIP-TSC, betamax, e, Accellera, UVM, OVM

Is Legacy Holding You Back? Harry Foster, Mentor’s Verification Chief Scientist, will take center stage to give live presentations on the pressing SoC verification issues as he highlights recent research he has been reporting on in his numerous blogs.  The first event will be held in San Jose, CA USA (18 October 2011) and the second event will be held in Reading, UK (15 November 2011). Harry has been … Read More

VMM, VIP-TSC, Accellera, UVM, OVM

Historical Perspective In my early days of standards development, I was intrigued how a standard went from the development phase to use phase.  New standards were heralded with great fanfare but were also followed very quickly with books and other material to allow the “mere mortal” to understand what the IEEE standards prose meant and how best to use it.  Everyone had their favorite VHDL book and … Read More

VITAL, VHDL, VMM, OVM, Accellera, UVM, UVM World, OVM World

System Standards Worlds Initiate Unification Accellera, who brought us SystemVerilog, and the Open SystemC Imitative (OSCI), who brought us SystemC have made known their intent to unite to form a single front-end electronic design automation (EDA) standards organization.  You can read their joint press release here. While this may come as a surprise to many, one thing has remained … Read More

SystemC, TLM, Accellera, 1666, UVM, OSCI, DAC, DATE

User Adoption of OVM Featured; Views on UVM Discussed The Mentor Graphics user group meeting, User-2-User, in Santa Clara is all set.  U2U will be held on 26 April 2011 at the Santa Clara Marriott and one of the tracks will feature functional verification after keynote presentations by Mentor’s CEO, Wally Rhines and Xilinx’s CTO, Ivo Bolsens. Registration for the event is open and is fee-free.  U2U … Read More

Functional Verification, OVM, Accellera, UVM, VIP, U2U

Standard Co-Emulation Modeling Interface (SCE-MI) 2.1 Improves Verification Productivity The Accellera Interface Technical Subcommittee (ITC) completed version 2.1 of the standard used to interface software and hardware-based verification technology.  With SCE-MI, models can be developed for simulation to run in an emulation environment and visa versa. The major addition to SCE-MI 2.1 is support … Read More

UVM, DVCon, EDSFair, Accellera, OVM, SCE-MI