Posted Dec 3, 2010, by Harry Foster
As the saying goes: Those who fail to plan, plan to fail. With that said, I am excited to announce a new module focused on Verification Planning, which has been one of the Verification Academy’s most-requested subjects for new content. The new Verification Planning module is delivered by our subject matter expert, who literally wrote the book on the subject, Peet James.
The goal of verification planning … Read More
Tags:
Functional Verification,
OVM,
Assertion-Based Verification,
Verification Methodology,
UVM,
Verification Academy
Posted Jul 26, 2010, by Ping Yeung
For years one of the objectives in EDA has been to make formal property checking easy to use and its results easy to understand. With the Automatic formal check feature in the June release of the 0-In Formal tool version 3.0, I think we have made significant progress in this area.
The feature, which predefines a set of assertion rules to look for design issues automatically, makes formal technology … Read More
Tags:
automatic formal check,
formal property checking,
Assertion-Based Verification,
SVA,
Formal Verification,
functional coverage
Posted Jun 7, 2010, by Ping Yeung
After spending years verifying ASICs with dynamic simulation, I started working on static verification 10 years ago in a startup called 0-In Design Automation. I firmly believe that static verification can complement dynamic simulation. Static verification uses synthesis and formal technologies to find bugs in the design. It does not rely on simulation stimulus. You do not need to exercise the bugs, … Read More
Tags:
Assertion-Based Verification,
CDC,
0-In,
DAC,
Formal
Posted Jun 3, 2010, by Harry Foster
I’d like to encourage you to attend the technical panel titled Bridging Pre-Silicon Verification and Post-Silicon Validation at this year’s DAC. The panel will be held on Tuesday, June 15, 2010 between 2:00 PM—4:00 PM.
Chair:
Alan Hu - Univ. of British Columbia, Vancouver, BC, Canada
Organizers:
Rajesh Galivanche - Intel Corp., Santa Clara, CA
Amir Nahir … Read More
Tags:
Assertion-Based Verification,
47DAC
Posted Dec 21, 2009, by Harry Foster
I’m excited. I’ve had the pleasure of knowing Cliff Cummings for many years, and I was honored a couple of years ago to have him write the foreword in a book that I published on assertions. Now, we have joined forces to do a set of seminars titled: “Assertion-Based Verification for FPGA and IC Design.” The first seminar will take place on January 19, 2010 in Santa Clara, CA, and you can register online … Read More
Tags:
Verification Academy,
Assertion-Based Verification
Posted Dec 14, 2009, by Harry Foster
I was recently quoted in an EDA DesignLine blog as saying that “it is a myth that ABV is a mainstream technology.” Actually, the original quote comes from an extended abstract I wrote for an invited tutorial at Computer-Aided Engineering (CAV) in 2008 titled Assertion-Based Verification: Industry Myths to Realities. My claim is based on the Farwest Research 2007 study that found approximately 37 percent … Read More
Tags:
Verification Academy,
Assertion-Based Verification
Posted Dec 6, 2009, by Harry Foster
The last industry project I worked on, before joining EDA, was an advanced chip set for a very large, high-end server product line. The project consisted of a large team, spanning multiple years, with numerous physical, design, and verification challenges. During the project’s postmortem, where all the various engineering teams get together to discuss what worked well and what did not, I overhead one … Read More
Tags:
Assertion-Based Verification
