Hi Everyone,
Just wanted to let you know that we just posted the PDF of the latest, Texas-Sized, DAC edition of Verification Horizons on the Verification Academy. In addition to my Editor’s Note, in which I liken what we do as verification engineers to my set-building experiences in local theatre groups, and brag about my daughter, you’ll find these fine articles:
Interviewing a Verification Engineer … Read More
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Posts tagged with 'DAC'
Download the standard now – at no charge
The IEEE Standards Association (IEEE-SA) has published the latest UPF 2.1 standard, officially called IEEE Standard for Design and Verification of Low-Power Integrated Circuits, many refer to it as IEEE 1801 or UPF for the Unified Power Format as this was the name Accellera had given it prior to transferring standardization responsibility and ongoing maintenance … Read More
UPF, DAC, IEEE 1801, Accellera, Low Power, IEEE Get, ieee standards association
Live & In-Person at DAC 2012!
Verification Academy, the brain child of Dr. Harry Foster, Chief Verification Scientist at Mentor Graphics, was live from the Design Automation Conference tradeshow floor this year. Harry is pictured to the right giving an update on his popular verification survey from the DAC tradeshow floor.
The Verification Academy, predominantly a web-based resource is a popular … Read More
Verification Academy, UVM Express, Tech Design Forum, ACE, AMS, Thales, UPF, UVM, ABV, Coverage Closure, iTBA, Low Power, DAC, OVM, ARM, Assertion-Based Verification, Formal, Doulos, Verification Trends
Accellera Ushers in Unified Coverage Interoperability Standard (UCIS)
For the past few months, Accellera’s Unified Coverage Interoperability Standards working group has completed and released a new standard that is destined to help boost verification productivity and efficiency. Verification teams use a variety of verification technologies, many times from different suppliers, to achieve their verification … Read More
Where might our paths cross?
It is always challenge to fit all the needed visits in during the Design Automation Conference (DAC). If you happen to like some of the same events I attend, then the chances are good our paths might cross in public.
Saturday and Sunday are busy with an Accellera Systems Initiative board meeting. Split across two days, Accellera board members will meet to conduct traditional … Read More
UPF, UCIS, UVM, DAC, EDAC, Accellera, Verification Academy, SystemC, TLM, Gary Smith
System Standards Worlds Initiate Unification
Accellera, who brought us SystemVerilog, and the Open SystemC Imitative (OSCI), who brought us SystemC have made known their intent to unite to form a single front-end electronic design automation (EDA) standards organization. You can read their joint press release here.
While this may come as a surprise to many, one thing has remained … Read More
After spending years verifying ASICs with dynamic simulation, I started working on static verification 10 years ago in a startup called 0-In Design Automation. I firmly believe that static verification can complement dynamic simulation. Static verification uses synthesis and formal technologies to find bugs in the design. It does not rely on simulation stimulus. You do not need to exercise the bugs, … Read More
Visit Booth 1383 – The hub of OVM/UVM Activity at DAC
The OVM World booth at the Design Automation Conference (#1383) will feature user and partner presentations on OVM/UVM, a live discussion by prominent verification experts and a Tuesday cocktail reception from
4:30 p.m. to 6:00 p.m.
The Open Verification Methodology (OVM) is the industry’s open and interoperable solution, guaranteed to run on … Read More
UVM, DAC, design automation conference, Accellera, ovmworld, flexray, OVM
UVM: Charting the New Territory
At this year’s DAC, Accellera introduces UVM (Universal Verification Methodology) to the world at its Tuesday breakfast and panel discussion. While Accellera may call this “Charting the New Territory,” it is not terra incognita to Mentor Graphics nor to tens of thousands of OVM users. UVM is at is simplest, just OVM. If you know OVM; you know UVM.
While OVM and … Read More
You Are Invited – Register Now!
(seating is limited)
Sunday, June 13
2:30pm - 6:00pm
Anaheim Hilton, California Ballroom A
Anaheim, California
www.nascug.org
On the Sunday before DAC, the North American SystemC User’s Group (NASCUG) will hold NASCUG XIII and they invites all DAC attendees to this special event featuring the latest advancements in sustainable and flexible solutions for ESL design.
As … Read More
Recent Posts
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- Part 1: The 2012 Wilson Research Group Functional Verification Study
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- Getting AMP’ed Up on the IEEE Low-Power Standard
- Prologue: The 2012 Wilson Research Group Functional Verification Study
- Even More UVM Debug in Questa 10.2
- IEEE Approves New Low Power Standard
- Verification Horizons DVCon Issue Now Available
- Get your IEEE 1800-2012 SystemVerilog LRM at no charge