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IEEE 1801™-2013 Enters Pre-Publish Phase The completion and approval of electronic design automation standards has seemed to be the order of the day for several months now.  Added to this list is the IEEE Standards Association (SA) approval of their newly revised low power standard (IEEE 1801™-2013).  The IEEE SA’s Review Committee (RevCom) unanimously recommended approval and that was confirmed by … Read More

UPF, Erich Marschner, IEEE 1801, DVCon, RevCom, Low Power

IEEE Std. 1800™-2012 Officially Ratified The IEEE Standards Association (SA) Standards Board (SASB) officially approved the latest SystemVerilog revision, Draft 6, as an IEEE standard.  The SASB Review Committee (RevCom) agenda and the SASB agenda include review and formal approval of the latest work by the IEEE Computer Society Design Automation Standards Committee’s (DASC) SystemVerilog Working Group … Read More

Muttiple Inheritance, RevCom, Assertions, Tom Fitzpatrick, UVM, Ben Cohen, Soft Constraints, Hard Constraints, IEEE SASB, Stu Sutherland, DASC, DVCon

Accellera Ushers in Unified Coverage Interoperability Standard (UCIS) For the past few months, Accellera’s Unified Coverage Interoperability Standards working group has completed and released a new standard that is destined to help boost verification productivity and efficiency.  Verification teams use a variety of verification technologies, many times from different suppliers, to achieve their verification … Read More

DAC, DVCon, Accellera, UCIS, UCDB

In his recent post on UVM: Some Thoughts Before DVCon, Dennis outlined some great ideas about what we think should happen next for UVM. His 3rd point, “UVM needs to bridge the system domain,” is particularly relevant given the newly-formed Accellera Systems Initiative. This is actually an area we’ve been contemplating for a while here at Mentor, and as Dennis indicated, we shared our thoughts on this … Read More

Verification Methodology, Verification Academy, Functional Verification, SystemC, DVCon, UVM Connect, UVM-1.1, UVM

It is time to talk about what happens next with UVM The Design and Verification Conference (DVCon) has become the premier event to discuss front-end design issues with an emphasis on verification.  If one listens to the Conversation Central interview of DVCon leadership it is clear how singularly important DVCon is.  As one of the three organizers of the UVM Tutorial on Monday, I know the conference … Read More

DATE Conference, DVCon, Accellera, UVM, SystemC

Wally Rhines DVCon 2011 Keynote Highlights Survey on Verification Languages OK, maybe it is not the Dawning of the Age of Aquarius, but Wally Rhines’ DVCon 2011 keynote did have a slide titled “SystemVerilog in the Ascendancy.”  It is not a word I see or use much.  In fact, Google labs’ “Book Ngram Viewer” shows ascendancy has been in decline since around 1825. It struck me that the title was tending … Read More

OVM, DVCon, VHDL, Wally Rhines, UVM, Verification

Open SystemC Initiative Tackles the Future If you have examined the DVCon program, you know that it is a week full of the Universal Verification Methodology (UVM).  And I certainly encourage those with an interest in UVM to attend the Monday tutorial and the technical conference the next few days.  But you may also want to bring a colleague to attend the SystemC Day activities. For SystemC Day at … Read More

UVM, Jim Hogan, NASCUG, DVCon, TLM, OSCI, SystemC

Standard Co-Emulation Modeling Interface (SCE-MI) 2.1 Improves Verification Productivity The Accellera Interface Technical Subcommittee (ITC) completed version 2.1 of the standard used to interface software and hardware-based verification technology.  With SCE-MI, models can be developed for simulation to run in an emulation environment and visa versa. The major addition to SCE-MI 2.1 is support … Read More

UVM, DVCon, EDSFair, Accellera, OVM, SCE-MI

UVM Layering Package updated from OVM Layering Package In an earlier blog post, I discussed a sequence layering technique that Mentor verification technologists had created and presented on at DVCon 2010, based on OVM.  This package has been updated and tested to work with UVM 1.0 EA and is ready for download. As a reminder, the UVM Layering 1.0 Package, like the OVM one, provides the means to add … Read More

OVM, Register Package, DVCon, testbench, UVM, Sequence, sequencers

Download Now A new OVM Layering Package that provides a means to add layers of tests (sequences) without modifying the underlying testbench and without extending components or using the factory to override implementation is available for download. The DVCon 2010 paper on this topic, You Are In a Maze of Twisty Little Sequences, All Alike – or Layering Sequences for Stimulus Abstraction, is also … Read More

layered sequences, OVM, DVCon, Register Package

SystemC User Group Meeting & DVCon Tutorial Featured The Open SystemC Initiative (OSCI), an independent non-profit organization dedicated to support and advance SystemC™ as an industry-standard language for electronic system-level (ESL) design, announced its lineup of events at DVCon 2010, most notably the first annual SystemC Day on Monday, Feb. 22. Mentor Graphics is one of the sponsors for the … Read More

DVCon, NASCUG, OSCI

Hi Gang, As you may know, in addition to my duties here at Mentor, I’m also the General Chair of DVCon 2010. So it is with two hats on that I encourage you to check out the DVCon website. With my “General Chair hat” on, I’d like to point out that we’ve actually expanded the conference to add an extra set of half-day tutorials on Monday afternoon, Feb. 22. That’s right! While other conferences are … Read More

OVM, DVCon

The inspiration for this week’s blog entry comes from a comment left by Jason Andrews from Cadence. Jason is an all around good guy who has been working this area of hardware and software for quite a few years, too. Here’s a link to his blog over in Cadence-land – Jason Andrew’s Blog. Anyway, Jason pointed out that the EDA companies need to get with the program and realize that software is a part … Read More

Seamless, DVCon