Posts tagged with 'OVM'
Standard Co-Emulation Modeling Interface (SCE-MI) 2.1 Improves Verification Productivity
The Accellera Interface Technical Subcommittee (ITC) completed version 2.1 of the standard used to interface software and hardware-based verification technology. With SCE-MI, models can be developed for simulation to run in an emulation environment and visa versa.
The major addition to SCE-MI 2.1 is support … Read More
As the saying goes: Those who fail to plan, plan to fail. With that said, I am excited to announce a new module focused on Verification Planning, which has been one of the Verification Academy’s most-requested subjects for new content. The new Verification Planning module is delivered by our subject matter expert, who literally wrote the book on the subject, Peet James.
The goal of verification planning … Read More
Functional Verification, OVM, Assertion-Based Verification, Verification Methodology, UVM, Verification Academy
Mentor/Synopsys Collaboration Bears Fruit
Two weeks back I shared information in a blog on collaboration between Mentor Graphics and Synopsys to reduce the number of candidate register packages being considered by the Accellera Verification IP (VIP) Technical Subcommittee (TSC). Mentor withdrew its candidate when all our requirements were able to be addressed in an update to the Synopsys RAL candidate.
As … Read More
Companion OVM Cookbook Examples Kit also offered for download
Several months ago, the OVM Cookbook and the Examples Kit were made available for online use at the Verification Academy. This proved to be a great help to accelerate the skill level of new OVM users. Given the number of new projects that have deployed OVM and the number of new engineers that now need to use OVM, there is increased demand … Read More
OVM, Verification Academy, cookbook, Verification Methodology
Mentor Announces Collaboration with Synopsys on Joint Register Package Candidate
Mentor has recently teamed with Synopsys to collaborate on the Synopsys RAL candidate to provide extensions that meet our register package requirements. Because of this, it allowed us to withdraw our candidate from consideration by the Accellera VIP-TSC recently.
Further, as part of the Accellera VIP-TSC UVM development … Read More
OVM, ral, Accellera, verification methodolgy, VIP-TSC, Register Package, UVM
Now that the Accellera VIP-TSC has released UVM-EA, effectively narrowing the choice of verification methodologies to UVM or OVM, many people are asking which way to go — OVM or UVM? The answer depends a lot on where you are in code development and what your risk tolerance is. The good news is that neither is a bad choice. One thing is certain: OVM is not dead yet. It will be around for a long time. … Read More
OVM, UVM, Accellera, UVM-1.0, VIP-TSC, UVM E.A., UVM Early Adopter
I’ve always loved the Chinese proverb, “Give a man a fish and you feed him for a day. Teach a man to fish and you feed him for a lifetime.” Yet, why merely settle for fish when you can have sushi! My point is, to remain strategically relevant in today’s competitive landscape, it is necessary to constantly reinvent ourselves and evolve our technical skills. To that end, we have created the Verification … Read More
DAC Attendees Invited to Accellera’s Breakfast sponsored by Mentor, Cadence & Synopsys
The full statement can be read at EDA Cafe, click here.
The Big-3 EDA companies point out in the statement the work within Accellera to create an interoperability guide and kit to ensure verification IP and testbenches written in either the Verification Methodology Manual (VMM) or the Open Verification Methodology … Read More
Visit Booth 1383 – The hub of OVM/UVM Activity at DAC
The OVM World booth at the Design Automation Conference (#1383) will feature user and partner presentations on OVM/UVM, a live discussion by prominent verification experts and a Tuesday cocktail reception from
4:30 p.m. to 6:00 p.m.
The Open Verification Methodology (OVM) is the industry’s open and interoperable solution, guaranteed to run on … Read More
UVM, DAC, design automation conference, Accellera, ovmworld, flexray, OVM
UVM: Charting the New Territory
At this year’s DAC, Accellera introduces UVM (Universal Verification Methodology) to the world at its Tuesday breakfast and panel discussion. While Accellera may call this “Charting the New Territory,” it is not terra incognita to Mentor Graphics nor to tens of thousands of OVM users. UVM is at is simplest, just OVM. If you know OVM; you know UVM.
While OVM and … Read More
UVM Layering Package updated from OVM Layering Package
In an earlier blog post, I discussed a sequence layering technique that Mentor verification technologists had created and presented on at DVCon 2010, based on OVM. This package has been updated and tested to work with UVM 1.0 EA and is ready for download.
As a reminder, the UVM Layering 1.0 Package, like the OVM one, provides the means to add … Read More
OVM, Register Package, DVCon, testbench, UVM, Sequence, sequencers
Mentor supplies the first Register Package for UVM
As I mentioned in my earlier blog post to disclose Mentor’s support of UVM-EA on the Questa Verification Platform, we would bring forward other OVM elements and make them UVM ready. We have done this for the OVM register package.
For those who are looking at the UVM-EA and want to avail themselves of additional UVM-ready value added elements, you … Read More
The Accellera VIP-TSC makes the Early Adopter release of the Universal Verification Methodology (UVM) available.
While Accellera does not use the Latin word Omnimodus in place of the English word Universal, what Accellera does make available is for all practical intents and purposes just OVM. In April 2010, we made available at www.ovmworld.org an early version of UVM EA. It has now been updated … Read More
Functional Verification, OVM, Accellera, VIP-TSC, UVM, UVM E.A.
Download Now
A new OVM Layering Package that provides a means to add layers of tests (sequences) without modifying the underlying testbench and without extending components or using the factory to override implementation is available for download.
The DVCon 2010 paper on this topic, You Are In a Maze of Twisty Little Sequences, All Alike – or Layering Sequences for Stimulus Abstraction, is also … Read More
In January 2010 we released the OVM 1.0 Register Package. It has now been updated to enhance capabilities and address issues raised by users. The updated contribution can be downloaded from OVM World.
The OVM 2.0 Register Package builds on 1.0 with new built-in register tests, easier cloning and copying of registers and register maps. The code has been ported to other implementations besides Questa.
A … Read More
