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Partners Offer Support for OVM 1.0 Register Package

Posted Feb 23, 2010, by Dennis Brophy

Duolog Joins Agnisys to Add Reg Pac Support The OVM 1.0 Register Package has had a lot of interest since uploaded a few weeks back. With more than 1,100 downloads and counting, it is being qualified for use and deployment in a growing number of user verification environments. Complementing the availability of the OVM 1.0 Register Package is support by partners with their applications that promote … Read More

Tags: Partner, Register Package, OVM

Dave Rich Featured on EEWeb
How Did I Get Here?
Expanding the Verification Academy!
Get on the Fast Track to Advanced Verification with UVM Express
Introducing UVM Connect
Tornado Alert!!!
UVM: Some Thoughts Before DVCon
UVM™ at DVCon 2012
SystemC 2011 Standard Published
Verification solutions that help reduce bug cost

May, 2012
- Dave Rich Featured on EEWeb
March, 2012
- How Did I Get Here?
February, 2012
- Expanding the Verification Academy!
- Get on the Fast Track to Advanced Verification with UVM Express
- Introducing UVM Connect
- Tornado Alert!!!
- UVM: Some Thoughts Before DVCon
- UVM™ at DVCon 2012
January, 2012
- SystemC 2011 Standard Published
- Verification solutions that help reduce bug cost
December, 2011
- Instant Replay for Debugging SoC Level Simulations
- 2011 IEEE Design Automation Standards Awards
November, 2011
- Overridden with Overrides
- Getting started with the UVM – Using the Register Modeling package
- TLM Becomes an IEEE Standard
October, 2011
- Be afraid, be very afraid
- Worlds Standards Day 2011
- VHS or Betamax?
- Verification Issues Take Center Stage
September, 2011
- New UVM Recipe-of-the-Month: Sequence Layering
July, 2011
- Combining Intelligent Testbench Automation with Constrained Random Testing
- Going from “Standards Development” to “Standards Practice”
- Verification Academy Now Includes OVMWorld Content
June, 2011
- Intelligent Testbench Automation Delivers 10X to 100X Faster Functional Verification
- Part 9: The 2010 Wilson Research Group Functional Verification Study
- Verification Horizons DAC Issue Now Available Online
- Accellera & OSCI Unite
- The IEEE's Most Popular EDA Standards
- UVM Register Kit Available for OVM 2.1.2
May, 2011
- I'd Like to Thank the Academy...
- Part 8: The 2010 Wilson Research Group Functional Verification Study
- Getting Your Standards Update @ DAC 2011
April, 2011
- User-2-User’s Functional Verification Track
- Part 7: The 2010 Wilson Research Group Functional Verification Study
- Part 6: The 2010 Wilson Research Group Functional Verification Study
- SystemC Day 2011 Videos Available Now
- Part 5: The 2010 Wilson Research Group Functional Verification Study
- Part 4: The 2010 Wilson Research Group Functional Verification Study
- Part 3: The 2010 Wilson Research Group Functional Verification Study
March, 2011
- Part 2: The 2010 Wilson Research Group Functional Verification Study
- Part 1: The 2010 Wilson Research Group Functional Verification Study
- Prologue: The 2010 Wilson Research Group Functional Verification Study
- Language Transitions: The Dawning of Age of Aquarius
- Using the UVM 1.0 Release with Questa
February, 2011
- DVCon: The Present and the Future
- Free at Last! UVM1.0 is Here!
- Hunting Multi-core Bugs
- IEEE Standards in India
January, 2011
- Accellera Approves New Co-Emulation Standard
December, 2010
- New Verification Horizons: Methodologies Don’t Have to be Scary
- The Survey Says: Verification Planning
October, 2010
- Towards UVM Register Package Interoperability
- IEC’s 47th General Assembly Meeting Opens
- UVM: Giving Users What They Want
September, 2010
- UVM Takes Shape in the Accellera VIP-TSC
- Accellera VIP-TSC Selects RAL for UVM 1.0 Register Package
- OVM Cookbook Available from OVMWorld.org
- UVM Register Package Candidate News
August, 2010
- Redefining Verification Performance (Part 2)
July, 2010
- Making formal property checking easy to use
- Redefining Verification Performance (Part 1)
- SystemVerilog Coding Guidelines: Package import versus `include
June, 2010
- The reports of OVM’s death are greatly exaggerated (with apologies to Mark Twain)
- New Verification Academy Advanced OVM (&UVM) Module
- The Dog That Didn’t Bark
- DAC: Day 1; An Ode to an Old Friend
- UVM: Joint Statement Issued by Mentor, Cadence & Synopsys
- Static Verification
- OVM/UVM at DAC 2010
- DAC Panel: Bridging Pre-Silicon Verification and Post-Silicon Validation
- Accellera’s DAC Breakfast & Panel Discussion
May, 2010
- Easier UVM Testbench Construction – UVM Sequence Layering
- North American SystemC User Group (NASCUG) Meeting at DAC
- An Extension to UVM: The UVM Container
- UVM Register Package 2.0 Available for Download
- Accellera’s OVM: Omnimodus Verification Methodology
- High-Level Design Validation and Test (HLDVT) 2010
- New OVM Sequence Layering Package – For Easier Tests
- OVM 2.0 Register Package Released
- OVM Extensions for Testbench Reuse
April, 2010
- SystemC Day Videos from DVCon Available Now
- On Committees and Motivations
- The Final Signatures (the meeting during the meeting)
- UVM Adoption: Go Native-UVM or use OVM Compatibility Kit?
- UVM-EA (Early Adopter) Starter Kit Available for Download
- Accellera Adopts OVM 2.1.1 for its Universal Verification Methodology (UVM)
March, 2010
- The Art of Deprecation
- OVM 2.1.1 Now Ready for Download
- February 2010 Verification Horizons Newsletter Now Available
- Emulation 104 -- Running More Tests in Less Time
- IEEE Standards Meetings in India
February, 2010
- Time to Power Diet!
- I Do It …
- SystemVerilog: A time for change? Maybe not.
- Partners Offer Support for OVM 1.0 Register Package
- SystemC Day at DVCon
- OVM/VMM Interoperability Kit: It’s Ready!
January, 2010
- Three Perfect 10’s
- Our OWL ran down the batteries after only 1 month !
- OVM 1.0 Register Package Released
- Accellera Adopts OVM
- SystemC (IEEE Std. 1666™) Comes to YouTube
- Debugging requires a multifaceted solution
- Getting the Most out of Your Directed Test Environment
December, 2009
- A Cliffhanger ABV Seminar, Jan 19, Santa Clara, CA
- Truth in Labelling: VMM2.0
- IEEE Std. 1800™-2009 (SystemVerilog) Ready for Purchase & Download
- December Verification Horizons Issue Out
- Evolution is a tinkerer
- It Is Better to Give than It Is to Receive
- Zombie Alert! (Can the CEDA DTC “User Voice” Be Heard When They Won’t Let You Listen)
- DVCon is Just Around the Corner
- The “Standards Corner” Becomes a Blog
- I Am Honored to Honor
- IEEE Standards Association Awards Ceremony
- ABV and people from Missouri...
- Time hogs, blogs, and evolving underdogs...
- Full House – and this is no gamble!
- Welcome to the Verification Horizons Blog!
November, 2009
- Bug Prospecting with Coverage-Aware Stimulus
October, 2009
- A Roll of the Dice
- Emulation 103--Accelerating Transaction-based Verification
September, 2009
- Porting Problems
- SystemVerilog: The finer details of $unit versus $root.
- SystemVerilog: The finer details of $unit versus $root.
- Guilty Pleasures
- Are You Covered?
- SystemVerilog Coding Guidelines
- SystemVerilog Coding Guidelines
- Can Software Find Hardware Bugs?
August, 2009
- Whose job is it, anyway?
- Emulation 102 – Emulation ROI – How can you not to invest in Emulation methodology?
- inFact - Easier Than Sudoku?
- Hello World
July, 2009
- Emulation 101 – SoC Emulation vs. Prototyping: What’s the Difference?
- The Language versus The Methodology
May, 2009
- Are Program Blocks Necessary?

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