More
Blog
Posts tagged with 'Simulation Server Farms'
Recent Posts
- Part 1: The 2012 Wilson Research Group Functional Verification Study
- Those nasty wire’s and reg’s in Verilog
- Getting AMP’ed Up on the IEEE Low-Power Standard
- Prologue: The 2012 Wilson Research Group Functional Verification Study
- Even More UVM Debug in Questa 10.2
- IEEE Approves New Low Power Standard
- Verification Horizons DVCon Issue Now Available
- Get your IEEE 1800-2012 SystemVerilog LRM at no charge
- IEEE 1800™-2012 SystemVerilog Standard Is Published
- See You at DVCon 2013!
Archives
- May, 2013
- April, 2013
- March, 2013
- February, 2013
- January, 2013
- December, 2012
- November, 2012
- October, 2012
- July, 2012
- June, 2012
- May, 2012
- March, 2012
- February, 2012
- January, 2012
- December, 2011
- November, 2011
- October, 2011
- September, 2011
- July, 2011
- June, 2011
- Intelligent Testbench Automation Delivers 10X to 100X Faster Functional Verification
- Part 9: The 2010 Wilson Research Group Functional Verification Study
- Verification Horizons DAC Issue Now Available Online
- Accellera & OSCI Unite
- The IEEE's Most Popular EDA Standards
- UVM Register Kit Available for OVM 2.1.2
- May, 2011
- April, 2011
- User-2-User’s Functional Verification Track
- Part 7: The 2010 Wilson Research Group Functional Verification Study
- Part 6: The 2010 Wilson Research Group Functional Verification Study
- SystemC Day 2011 Videos Available Now
- Part 5: The 2010 Wilson Research Group Functional Verification Study
- Part 4: The 2010 Wilson Research Group Functional Verification Study
- Part 3: The 2010 Wilson Research Group Functional Verification Study
- March, 2011
- February, 2011
- January, 2011
- December, 2010
- October, 2010
- September, 2010
- August, 2010
- July, 2010
- June, 2010
- The reports of OVM’s death are greatly exaggerated (with apologies to Mark Twain)
- New Verification Academy Advanced OVM (&UVM) Module
- The Dog That Didn’t Bark
- DAC: Day 1; An Ode to an Old Friend
- UVM: Joint Statement Issued by Mentor, Cadence & Synopsys
- Static Verification
- OVM/UVM at DAC 2010
- DAC Panel: Bridging Pre-Silicon Verification and Post-Silicon Validation
- Accellera’s DAC Breakfast & Panel Discussion
- May, 2010
- Easier UVM Testbench Construction – UVM Sequence Layering
- North American SystemC User Group (NASCUG) Meeting at DAC
- An Extension to UVM: The UVM Container
- UVM Register Package 2.0 Available for Download
- Accellera’s OVM: Omnimodus Verification Methodology
- High-Level Design Validation and Test (HLDVT) 2010
- New OVM Sequence Layering Package – For Easier Tests
- OVM 2.0 Register Package Released
- OVM Extensions for Testbench Reuse
- April, 2010
- SystemC Day Videos from DVCon Available Now
- On Committees and Motivations
- The Final Signatures (the meeting during the meeting)
- UVM Adoption: Go Native-UVM or use OVM Compatibility Kit?
- UVM-EA (Early Adopter) Starter Kit Available for Download
- Accellera Adopts OVM 2.1.1 for its Universal Verification Methodology (UVM)
- March, 2010
- February, 2010
- January, 2010
- December, 2009
- A Cliffhanger ABV Seminar, Jan 19, Santa Clara, CA
- Truth in Labelling: VMM2.0
- IEEE Std. 1800™-2009 (SystemVerilog) Ready for Purchase & Download
- December Verification Horizons Issue Out
- Evolution is a tinkerer
- It Is Better to Give than It Is to Receive
- Zombie Alert! (Can the CEDA DTC “User Voice” Be Heard When They Won’t Let You Listen)
- DVCon is Just Around the Corner
- The “Standards Corner” Becomes a Blog
- I Am Honored to Honor
- IEEE Standards Association Awards Ceremony
- ABV and people from Missouri...
- Time hogs, blogs, and evolving underdogs...
- Full House – and this is no gamble!
- Welcome to the Verification Horizons Blog!
- November, 2009
- October, 2009
- September, 2009
- August, 2009
- July, 2009
- May, 2009
Tags
- UVM (39)
- OVM (38)
- Accellera (30)
- Functional Verification (22)
- Verification (17)
- Verification Academy (17)
- DVCon (13)
- SystemC (12)
- Assertion-Based Verification (9)
- VIP-TSC (8)
- OSCI (8)
- VHDL (8)
- DAC (8)
- testbench (8)
- Register Package (8)
- TLM (7)
- Verification Methodology (7)
- 1666 (6)
- IEEE 1800 (6)
- UPF (6)
- ARM (5)
- VMM (5)
- Formal Verification (5)
- Verilog (5)
- functional coverage (5)
- SoC (4)
- UVM E.A. (4)
- Low Power (4)
- Intelligent Testbench Automation (4)
- 1076 (3)
- 1364 (3)
- iTBA (3)
- IEEE 1801 (3)
- Coverage Closure (3)
- UCIS (3)
- Questa (3)
- Debug (3)
- DASC (3)
- NASCUG (3)
- VIP (3)
- Add new tag (3)
- EDAC (2)
- inFact (2)
- 47DAC (2)
- CAG (2)
- Wally Rhines (2)
- Formal (2)
- Jim Hogan (2)
- ral (2)
- UVM Cookbook (2)
- UCDB (2)
- RevCom (2)
- VITAL (2)
- UVM Early Adopter (2)
- iec (2)
- Harry Foster (2)
- Coverage Cookbook (2)
- Constrained Random Test (2)
- Multicore (2)
- Emulation (2)
- EDSFair (2)
- AMS (2)
- configuration (1)
- TLM 1.0 (1)
- Verification Trends (1)
- Seamless (1)
- dual-logo (1)
- UC Davis (1)
- Tom Fitzpatrick (1)
- UVM-1.0 (1)
- DPI (1)
- VHS (1)
- Tech Design Forum (1)
- Directed Test Environment (1)
- Testbench Simulation (1)
- Jim Aynsley (1)
- Don Loughry (1)
- Coverage (1)
- design automation conference (1)
- e (1)
- UVM Express (1)
- Erich Marschner (1)
- UVM Connect (1)
- IoT (1)
- sequencers (1)
- verification IP (1)
- 1801 (1)
- Veloce (1)
- ARM TechCon (1)
- denali (1)
- CDC (1)
- OVM World (1)
- Accellera Systems Initiative (1)
- Verification Acdemy (1)
- WG2 (1)
- SCE-MI (1)
- Crossing the Chasam (1)
- Sequence (1)
- cookbook (1)
- Stimulus-Coverage Closure (1)
- Verification Horizons (1)
- Spirit (1)
- SVA (1)
- Interoperability (1)
- 1666-2005 (1)
- Instant Replay (1)
- JEITA (1)
- IEEE SASB (1)
- formal property checking (1)
- Software as a Testbench (1)
- Doulos (1)
- Randomly-Generated Stimulus (1)
- 1076.4 (1)
- Hewlett-Packard (1)
- Assertions (1)
- synopsys (1)
- virtual interface (1)
- cci (1)
- Cortex (1)
- ACE (1)
- Award (1)
- Constrained Random (1)
- Wilson Research Group Study (1)
- Lan (1)
- Stu Sutherland (1)
- interoperability forum (1)
- VPI (1)
- TLM 2.0 (1)
- Power Aware Verification (1)
- esl (1)
- 488 (1)
- ovmworld (1)
- PLI (1)
- betamax (1)
- Thales (1)
- Convergence (1)
- TC93 (1)
- Ethernet (1)
- flexray (1)
- 1735 (1)
- IEEE Get (1)
- UVM-1.1 (1)
- oneM2M (1)
- 0-In (1)
- UVM World (1)
- proof-of-concept library (1)
- ieee 1076 (1)
- Partner (1)
- tracing (1)
- Tipping Point (1)
- Internet of Things (1)
- Partners (1)
- open-source (1)
- Muttiple Inheritance (1)
- The SPIRIT Consortium (1)
- layered sequences (1)
- DATE Conference (1)
- Uncategorized (1)
- Constrained-Random Stimulus (1)
- DATE (1)
- Hard Constraints (1)
- automatic formal check (1)
- verification methodolgy (1)
- 1666-2011 (1)
- JTAG (1)
- Coverage-Driven Stimulus (1)
- IP-XACT (1)
- Gary Smith (1)
- Soft Constraints (1)
- Debugging (1)
- SoC Level Verification (1)
- ABV (1)
- VIP-TC (1)
- Methodology (1)
- Business Model (1)
- U2U (1)
- HP-IB (1)
- Ben Cohen (1)
Twitter Updates
RT @CalyptoDesign: Read Shawn McCloud's article "Raising the Bar for Power Optimization" in Chip Design. #DAC50 #Power #EDA #SemiEDA http:/… 6:30 AM May 18
RT @dave_59: What's the deal with those wire's and reg's in #Verilog and #SystemVerilog. http://t.co/520olnyog4 6:26 AM May 18
What's the deal with those wire's and reg's in #Verilog and #SystemVerilog. http://t.co/520olnyog4 7:20 AM May 13
My DAC moment http://t.co/LA5S97gDQU #SemiEDA #Verilog 2:57 PM May 9