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Posts tagged with 'SoC'

Tornado Alert!!!

Posted Feb 21, 2012, by Dennis Brophy

Is my car trying to tell me something? This past Friday was the beginning of a two day internal functional verification meeting at Mentor Graphics corporate headquarters on Intelligent Testbench Automation (iTBA).  (Mentor’s iTBA product, Questa inFact is hot and getting hotter.) After getting to my car to return home at the end of the first day, I was thinking that the large interest in this technology … Read More

Tags: UVM, Tipping Point, Veloce, inFact, Intelligent Testbench Automation, Crossing the Chasam, Questa, SoC, iTBA, OVM

Instant Replay for Debugging SoC Level Simulations

Posted Dec 13, 2011, by Mark Olen

Instant Replay Offers Multiple Views at Any Speed If you’ve watched any professional sporting event on television lately, you’ve seen the pressure put on referees and umpires.  They have to make split-second decisions in real-time, having viewed ultra-high-speed action just a single time.  But watching at home on television, we get the luxury of viewing multiple replays of events in question … Read More

Tags: Verification, testbench, Software as a Testbench, SoC, Functional Verification, Cortex, SoC Level Verification, ARM

SystemC Day 2011 Videos Available Now

Posted Apr 15, 2011, by Dennis Brophy

Watch DVCon Co-Located Event Presentations Two presentations from the second annual SystemC Day at DVCon 2011 are available now.  The first presentation is the keynote by Jim Hogan, serial EDA entrepreneur at Vista Ventures, LLC and the second is an introduction to the emerging IEEE Std. 1666™, SystemC standard by Jim Aynsley at Doulos.  SystemC Day brought users together to discuss the current state … Read More

Tags: SystemC, esl, 1666, OSCI, SoC, Jim Aynsley, Jim Hogan

Emulation 103--Accelerating Transaction-based Verification

Posted Oct 7, 2009, by Ralph Zak

Transaction-Based Verification is a technique for verifying modern SoC designs with interfaces such as PCI express, using test benches at the transaction level of abstraction. Transaction-based verification complements directed and constrained random tests, and is an emerging methodology for verifying complex SoCs that have multiple on-chip standard bus and peripheral interfaces. Typically in a transaction-based … Read More

Tags: TBV, System on Chip, Transaction-Based Verification, Emulation, FPGA Prototyping, ASIC Emulation, SoC, SoC Verification, Simulation Server Farms

Emulation 101 – SoC Emulation vs. Prototyping: What’s the Difference?

Posted Jul 20, 2009, by Ralph Zak

This is my first blog posting about SoC Emulation for verification of SoC designs.  To set the stage, along with my biases, I am currently employed by Mentor Graphics and responsible for business development in the Emulation Division. I am an un-apologetic, evangelist for hardware-based verification. My experiences with hardware assisted verification began with simulation accelerators in the 80’s … Read More

Tags: SoC Prototyping, SoC Emulation, ASIC Emulation, ASIC Verification, EDA, Prototyping, SoC, FPGA Boards, FPGA Prototyping