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Verification Horizons Blog

Posts tagged with 'UVM'

21 Apr, 2011

Dennis Brophy User Adoption of OVM Featured; Views on UVM Discussed The Mentor Graphics user group meeting, User-2-User, in Santa Clara is all set.  U2U will be held on 26 April 2011 at the Santa Clara Marriott and one of the tracks will feature functional verification after keynote presentations by Mentor’s CEO, Wally Rhines and Xilinx’s CTO, Ivo Bolsens. Registration for the event is open and is fee-free.  U2U … Read More

Functional Verification, OVM, Accellera, UVM, VIP, U2U

25 Mar, 2011

Dennis Brophy Wally Rhines DVCon 2011 Keynote Highlights Survey on Verification Languages OK, maybe it is not the Dawning of the Age of Aquarius, but Wally Rhines’ DVCon 2011 keynote did have a slide titled “SystemVerilog in the Ascendancy.”  It is not a word I see or use much.  In fact, Google labs’ “Book Ngram Viewer” shows ascendancy has been in decline since around 1825. It struck me that the title was tending … Read More

OVM, DVCon, VHDL, Wally Rhines, UVM, Verification

22 Feb, 2011

DVCon: The Present and the Future

Posted by Dennis Brophy

Dennis Brophy Open SystemC Initiative Tackles the Future If you have examined the DVCon program, you know that it is a week full of the Universal Verification Methodology (UVM).  And I certainly encourage those with an interest in UVM to attend the Monday tutorial and the technical conference the next few days.  But you may also want to bring a colleague to attend the SystemC Day activities. For SystemC Day at DVCon, … Read More

UVM, Jim Hogan, NASCUG, DVCon, TLM, OSCI, SystemC

28 Jan, 2011

Dennis Brophy Standard Co-Emulation Modeling Interface (SCE-MI) 2.1 Improves Verification Productivity The Accellera Interface Technical Subcommittee (ITC) completed version 2.1 of the standard used to interface software and hardware-based verification technology.  With SCE-MI, models can be developed for simulation to run in an emulation environment and visa versa. The major addition to SCE-MI 2.1 is support for … Read More

UVM, DVCon, EDSFair, Accellera, OVM, SCE-MI

3 Dec, 2010

Harry Foster As the saying goes: Those who fail to plan, plan to fail. With that said, I am excited to announce a new module focused on Verification Planning, which has been one of the Verification Academy’s most-requested subjects for new content. The new Verification Planning module is delivered by our subject matter expert, who literally wrote the book on the subject, Peet James. The goal of verification planning … Read More

Functional Verification, OVM, Assertion-Based Verification, Verification Methodology, UVM, Verification Academy

14 Oct, 2010

Dennis Brophy 23rd Synopsys EDA Interoperability Forum Features a Verification Session with focus on the UVM Register Package As readers of the Verification Horizons BLOG know from recent posts, progress towards a register & memory facility in UVM 1.0 is well underway.  While the Accellera VIP-TSC is making good progress, limited information is available to non-participants.  This limited knowledge is true for … Read More

interoperability forum, Register Package, Accellera, UVM, VIP-TSC, synopsys

23 Sep, 2010

Dennis Brophy Mentor/Synopsys Collaboration Bears Fruit Two weeks back I shared information in a blog on collaboration between Mentor Graphics and Synopsys to reduce the number of candidate register packages being considered by the Accellera Verification IP (VIP) Technical Subcommittee (TSC).  Mentor withdrew its candidate when all our requirements were able to be addressed in an update to the Synopsys RAL candidate. As … Read More

OVM, ral, Accellera, UVM, VIP-TSC

7 Sep, 2010

UVM Register Package Candidate News

Posted by Dennis Brophy

Dennis Brophy Mentor Announces Collaboration with Synopsys on Joint Register Package Candidate Mentor has recently teamed with Synopsys to collaborate on the Synopsys RAL candidate to provide extensions that meet our register package requirements.  Because of this, it allowed us to withdraw our candidate from consideration by the Accellera VIP-TSC recently. Further, as part of the Accellera VIP-TSC UVM development … Read More

OVM, ral, Accellera, verification methodolgy, VIP-TSC, Register Package, UVM

28 Jun, 2010

Mark Glasser Now that the Accellera VIP-TSC has released UVM-EA, effectively narrowing the choice of verification methodologies to UVM or OVM, many people are asking which way to go — OVM or UVM?  The answer depends a lot on where you are in code development and what your risk tolerance is.  The good news is that neither is a bad choice. One thing is certain: OVM is not dead yet.  It will be around for a long time.  … Read More

OVM, UVM, Accellera, UVM-1.0, VIP-TSC, UVM E.A., UVM Early Adopter

9 Jun, 2010

Dennis Brophy DAC Attendees Invited to Accellera’s Breakfast sponsored by Mentor, Cadence & Synopsys The full statement can be read at EDA Cafe, click here. The Big-3 EDA companies point out in the statement the work within Accellera to create an interoperability guide and kit to ensure verification IP and testbenches written in either the Verification Methodology Manual (VMM) or the Open Verification Methodology … Read More

VMM, VIP, OVM, Accellera, verification IP, UVM

3 Jun, 2010

OVM/UVM at DAC 2010

Posted by Dennis Brophy

Dennis Brophy Visit Booth 1383 – The hub of OVM/UVM Activity at DAC The OVM World booth at the Design Automation Conference (#1383) will feature user and partner presentations on OVM/UVM, a live discussion by prominent verification experts and a Tuesday cocktail reception from 4:30 p.m. to 6:00 p.m. The Open Verification Methodology (OVM) is the industry’s open and  interoperable solution, guaranteed to run on … Read More

UVM, DAC, design automation conference, Accellera, ovmworld, OVM

2 Jun, 2010

Dennis Brophy UVM: Charting the New Territory At this year’s DAC, Accellera introduces UVM (Universal Verification Methodology) to the world at its Tuesday breakfast and panel discussion.  While Accellera may call this “Charting the New Territory,” it is not terra incognita to Mentor Graphics nor to tens of thousands of OVM users.  UVM is at is simplest, just OVM.  If you know OVM; you know UVM. While OVM and … Read More

Accellera, DAC, 47DAC, UVM, OVM

28 May, 2010

Dennis Brophy UVM Layering Package updated from OVM Layering Package In an earlier blog post, I discussed a sequence layering technique that Mentor verification technologists had created and presented on at DVCon 2010, based on OVM.  This package has been updated and tested to work with UVM 1.0 EA and is ready for download. As a reminder, the UVM Layering 1.0 Package, like the OVM one, provides the means to add … Read More

OVM, Register Package, DVCon, testbench, UVM, Sequence, sequencers

21 May, 2010

An Extension to UVM: The UVM Container

Posted by Dennis Brophy

Dennis Brophy Easier DUT to Testbench Connections This package introduces a very simple class called uvm_container. In this package Mentor shows how to use this class to link a Design Under Test (DUT) and a testbench.  The UVM Container can be downloaded here as a companion to the Accellera UVM 1.0 EA. This extension also introduces the dual top methodology. This methodology isolates the connections between the … Read More

UVM, Verification Methodology, Accellera

19 May, 2010

Dennis Brophy Mentor supplies the first Register Package for UVM As I mentioned in my earlier blog post to disclose Mentor’s support of UVM-EA on the Questa Verification Platform, we would bring forward other OVM elements and make them UVM ready.  We have done this for the OVM register package. For those who are looking at the UVM-EA and want to avail themselves of additional UVM-ready value added elements, you … Read More

Questa, Register Package, OVM, UVM

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