Legacy’s Luster Lost
As a follow-on to my last blog, where I shared information about Harry Foster speaking live about the research he has been reporting on the last year and where I noted legacy might hold some back, I was going to finish on some of the work we have done at Mentor Graphics to move forward while trying to keep some of those held back by legacy, whole.
Buy why this title? For some, … Read More
Tags: VHS, Verification, VIP-TSC, betamax, e, Accellera, UVM, OVM
Is Legacy Holding You Back?
Harry Foster, Mentor’s Verification Chief Scientist, will take center stage to give live presentations on the pressing SoC verification issues as he highlights recent research he has been reporting on in his numerous blogs. The first event will be held in San Jose, CA USA (18 October 2011) and the second event will be held in Reading, UK (15 November 2011).
Harry has been … Read More
23rd Synopsys EDA Interoperability Forum Features a Verification Session with focus on the UVM Register Package
As readers of the Verification Horizons BLOG know from recent posts, progress towards a register & memory facility in UVM 1.0 is well underway. While the Accellera VIP-TSC is making good progress, limited information is available to non-participants. This limited knowledge is true for … Read More
Tags: interoperability forum, Register Package, Accellera, UVM, VIP-TSC, synopsys
Mentor/Synopsys Collaboration Bears Fruit
Two weeks back I shared information in a blog on collaboration between Mentor Graphics and Synopsys to reduce the number of candidate register packages being considered by the Accellera Verification IP (VIP) Technical Subcommittee (TSC). Mentor withdrew its candidate when all our requirements were able to be addressed in an update to the Synopsys RAL candidate.
As … Read More
Mentor Announces Collaboration with Synopsys on Joint Register Package Candidate
Mentor has recently teamed with Synopsys to collaborate on the Synopsys RAL candidate to provide extensions that meet our register package requirements. Because of this, it allowed us to withdraw our candidate from consideration by the Accellera VIP-TSC recently.
Further, as part of the Accellera VIP-TSC UVM development … Read More
Tags: OVM, ral, Accellera, verification methodolgy, VIP-TSC, Register Package, UVM
Now that the Accellera VIP-TSC has released UVM-EA, effectively narrowing the choice of verification methodologies to UVM or OVM, many people are asking which way to go — OVM or UVM? The answer depends a lot on where you are in code development and what your risk tolerance is. The good news is that neither is a bad choice. One thing is certain: OVM is not dead yet. It will be around for a long time. … Read More
Tags: OVM, UVM, Accellera, UVM-1.0, VIP-TSC, UVM E.A., UVM Early Adopter
The Accellera VIP-TSC makes the Early Adopter release of the Universal Verification Methodology (UVM) available.
While Accellera does not use the Latin word Omnimodus in place of the English word Universal, what Accellera does make available is for all practical intents and purposes just OVM. In April 2010, we made available at www.ovmworld.org an early version of UVM EA. It has now been updated … Read More
Tags: Functional Verification, OVM, Accellera, VIP-TSC, UVM, UVM E.A.
3 – 2 – 1 – DOWNLOAD!
As I mentioned in a previous blog, the Accellera OVM/VMM Interoperability kit code that is a companion to the Verification Intellectual Property Recommended Practices (1MB PDF) was nearing readiness. As of today, it is now ready for download and use. With qualification tests run on verification platforms from the Big-3 EDA companies, no objection was voiced at a recent Accellera … Read More
