Coverage-Driven Verification

  • Functional coverage metrics are used to automatically record and analyze information to ascertain whether a particular test verified a give feature, greatly enhancing predictability
  • Functionality targeted by directed tests is knows
  • SystemVerilog and PSL coverage features are used to generate and then take recorded information back into the process to target additional verification efforts more effectively
  • Efficient use of resources by eliminating or reducing the use of redundant tests

Coverage Driven Verification


Products

  • Questa AFV (Advanced Functional Verification)

    The first standards-based, single-kernel verification platform that integrates an HDL simulator, a constraint solver, an assertion engine, functinal coverage and a common user interface.  The platform also offers built-in support for testbench automation (TBA). cpmverage-driven verification (CDV), assertion-based verification (AVB), and transaction-level modeling (TML).

  • Questa SV (SystemVerilog)

    The first SystemVerilog, single-kernel verification environment wth a constraint solver, an assertion engine, functional coverage and a common user interface.  Questa SV also provides a complete SystemVerilog design environment and built-in support for testbench automation (TBA), coverage-driven verification (CDV), and assertion-based verification (ABV).

  • 0-In® Assertion Synthesis
    Complete ABV solution, including Verification IP, static checkers, analysis, and management.
  • 0-In Formal Verification
    Industry's most powerful static and dynamic formal verification environment
  • 0-In® CheckerWare®
    Verification IP monitor library for interconnect, processor buses, switch fabric, memories, and networking applications.
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