0-In® CheckerWare®

Designers are rapidly adopting assertion-based verification (ABV) as  the means to improve overall verification quality. The fastest way to adopt ABV  is through proven assertion libraries.  Assertion  libraries allow designers to simply select from a library the various design  intent checkers and protocol monitors and add them to the design without the  need to learn new languages and/or spend a lot of effort in creating these  checkers and monitor themselves.

The 0-In® Checkerware® Assertion Library dramatically improves the  productivity of assertion-based verification.  It consists of the industries largest set of design intent  checkers and monitors for a variety of industry standard protocols. All the  assertions can be used in simulation, emulation and/or FPGAs and formal  verification.

 
• Design  intent checking assertions include:
  • basic (driven, known, known_driven,  three_state)
  • interface (assert_follower,  assert_timer, bus_driver, change_timer)
  • control (channel_data_integrity,  multi_port_memory_access)
  • interface and control (assert_together,  multi_clock_fifo, scoreboard)
  • datapath (arithmetic_overflow,  data_used, encoder, serial_to_parallel)

• Protocol  monitors include:
  • Standard buses: AMBA (AHB, APB, AXI), OCP,
  • Interfaces: PCI, USB 1.1, PCI-X, USB  2.0, SATA, 10G  Ethernet, SCSI, 
  • Memory: AGP, DDR SDRAM, SRAM, DDR-II SDRAM, , SigmaRAM, 
  • Networking: UTOPIA, QDR, SPI4-2, , POS-PHY Level  2
   

Benefits

 
• Automatic coverage collection to quickly  identify verification holes
• Total interoperability with all standard  assertion formats, including PSL, SVA, and OVL
• Advanced management of checkers and  assertions throughout design lifecycle
• Unique design inference capability for  ease of adoption and maintainability of assertions

Supports simulators, emulators, and formal  verification tools from Mentor Graphics and third parties