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Certe Testbench Studio

UVM and OVM Testbench Creation and Analysis with Register Assistant Technology

Certe Testbench Studio delivers a powerful Eclipse-based environment that enables rapid creation and complete understanding of UVM and OVM based testbenches.

Certe Testbench Studio enables hardware and verification engineers to harness the power of UVM / OVM / SystemVerilog by guiding the development of testbenches and registers that are correct-by-construction. Certe augments creation with analysis through deep insight into testbench construction and functionality via connectivity diagrams, multiple class relationship views, and full testbench object browsers.

The Register Assistant technology delivers register specification and management, extending Certe’s correct-by-construction functionality by automatically generating registers and memories in the formats required by the various design disciplines on the project. The power of the Register Assistant technology expands to automating the production of register documentation, a critical part of today’s designs.

Benefits and Features

  • Increase productivity in the creation and analysis of extensible testbenches and project register specification
  • Design correct-by-construction testbenches and registers
  • Deploy OVM / UVM in a consistent, repeatable manner
  • Easily develop and reuse VIP
  • Generate consistency in testbench coding
  • Reduce testbench development and debug time
  • Analyze complex testbenches to improve comprehension
  • Automate builds
  • Generate documentation
  • Part of the Mentor Graphics advanced verification flow including ReqTracer™, Vista™, Questa® Functional Verification Platform, and HDL Designer™
  • Eclipse-based for extensibility
  • Flexible and scalable Template Code Generators
  • “Smart” UVM / OVM code editor
  • Visualization of static code and simulated testbench structure
  • Analysis of class composition, inheritance and relationships
  • UVM, OVM and verification compliance rule checks
  • UVM, OVM, AVM and SystemVerilog support
  • Automatic generation of customized Makefile
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