Certus™ ASIC Prototyping Debug Solution is now part of the Design Verification and Technology Division of Mentor Graphics!

We are excited to add the Certus solution to our portfolio of design verification and validation solutions. By delivering the highest possible number of verification cycles pre-silicon manufacturing, FPGA prototyping of ASICs has become an integral part of SoC design and verification flows.

Certus addresses the greatest challenge in FPGA prototyping: Observability and debug of the SoC design within the FPGA prototype. Certus stands alone in providing the most flexible, lowest resource cost, highest productivity silicon observability with trace depth capacity capable of observing and debugging complex system-level interactions.