Questa Codelink

Codelink is an advanced debug toolset for functional verification of processor-based designs using your RTL or gate-level processor models. Codelink aids processor-driven verification by dramatically improving processor visibility and reducing the time it takes to debug failing processor-driven tests. It connects to existing processor signoff models without changing the design or simulation results.

Effortless Debug

Just imagine. No more slogging through the processor instruction trace log, symbol tables, and assembly listings to debug a failing batch run. During simulation Codelink records a processor state log-file and delivers post-simulation, interactive debug of the processor state 100% correlated with the hardware waveforms. A lengthy batch simulation can be replayed in seconds, eliminating the need to re-simulate a failing test in order to debug it.

Once you have more confidence in the hardware design, move up to Codelink Pro and to Seamless for improved integration of hardware and software.

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Easily Inspect & Find Defects in Your Processor-Based Design and Testbench

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Questa Codelink Pro

Codelink Pro is an advanced debug toolset for functional verification of processor-based designs using cycle-based processor models. Codelink Pro makes processor driven verification effective by dramatically reducing the time it takes to integrate software with hardware.

It delivers graphical, source-level debug for software executing on a cycle-based, fully functional processor model that is connected to the system running in a logic simulator. After verifying your processor-based hardware design with Codelink, you’ll want to move to Codelink Pro to gain higher performance as you verify hardware/software interaction. Codelink Pro decreases the overall simulation time by orders of magnitude compared to logic simulation speeds. During simulation Codelink Pro records a software log-file and delivers highly interactive, post-simulation HW/SW debug. In addition to interactive debug during simulation, a lengthy batch simulation can be replayed in seconds, eliminating the need to re-simulate a failing test in order to debug it.

Faster simulation results for integrating software and hardware are delivered by moving the simulation of the processor to a higher level of abstraction. The increased simulation speed is achieved by replacing the fully functional design sign-off model or RTL processor(s) in the design with a processor support package (PSP) based on a vendor-supplied processor model that runs faster than RTL.

Move up to Seamless for greater flexibility and control of your hardware and software integration environment.

Benefits

  • Immediate productivity. Codelink requires no changes to your design. Add a command line argument to the simulator invocation and you are up and running in less than 30 minutes
  • Increase Hardware Debug Efficiency. Reduces hardware debug time for processor-driven tests by 50-80%
  • Non-intrusive. Zero impact to simulation results and accuracy to all designs including low power designs
  • Full Visibility. Register, software variable, memory, and call stack views 100% synchronized with hardware logic waveforms
  • Effective Processor Driven Verification. Isolates processor-driven test failures in minutes. Supports C, C++, and assembly code
  • Multi-core designs. Debug multi-core synchronization errors
  • Interactive. Move instantly to any point in the simulation log with fully synchronized hardware logic and processor debug visibility. Replay overnight simulations in seconds
  • Powerful Debug. Step forward and backward to see how you got here and what hardware was doing
  • Interactive, post-simulation debug of batch and regression runs
  • Graphical debug of processor state along with logic waveforms
  • Steps forward and backwards through processor instructions and hardware waveforms
  • 100% synchronization of processor state and hardware waveform views
  • Simultaneously monitors multiple processors in a multi-core design
  • Compatible with your RTL and fully functional compiled design sign-off model processor representations
  • Supports ARM, MIPS, and PowerPC processors

Related Products

  • Seamless Seamless enables users to debug hardware/software integration issues early in the design cycle by running embedded software on a simulation model of the embedded hardware.
  • Questa Questa is Mentor Graphic's Advanced Verification Environment and is the only integrated verification platform that can improve quality, productivity, and predictability for any verification flow.
  • ModelSim ModelSim combines high performance and high capacity with the code coverage and debugging capabilities required to simulate larger blocks and systems and attain ASIC gate-level sign-off. Comprehensive support of Verilog, VHDL, and SystemC provide a solid foundation for single and multi-language design verification environments.

From the Blogs

A Roll of the Dice

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blog post: Constrained random seems all the rage recently.    Last week I was visiting one of our field offices.  I was discussing with some of the applications engineers about how to use a processor to drive stimulus…View Blog Post

Porting Problems

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blog post: They say one of the first steps to fixing a problem is to acknowledge that you have one. Hi, I’m Russ, and I have a porting problem. If you work on software in the embedded world, you probably have a…View Blog Post

Guilty Pleasures

Russ Klein's Blog

blog post: You know you shouldn’t, but you do. I do. We all do. Though we don’t like to admit it. Yes, I use print statements to debug my code. And I work on debug tools for programmers and hardware engineers. I guess…View Blog Post

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