Questa Codelink

Codelink Pro is an advanced debug toolset for functional verification of processor-based designs using cycle-based processor models. Codelink Pro makes processor driven verification effective by dramatically reducing the time it takes to integrate software with hardware.

It delivers graphical, source-level debug for software executing on a cycle-based, fully functional processor model that is connected to the system running in a logic simulator. After verifying your processor-based hardware design with Codelink, you’ll want to move to Codelink Pro to gain higher performance as you verify hardware/software interaction. Codelink Pro decreases the overall simulation time by orders of magnitude compared to logic simulation speeds. During simulation Codelink Pro records a software log-file and delivers highly interactive, post-simulation HW/SW debug. In addition to interactive debug during simulation, a lengthy batch simulation can be replayed in seconds, eliminating the need to re-simulate a failing test in order to debug it.

Faster simulation results for integrating software and hardware are delivered by moving the simulation of the processor to a higher level of abstraction. The increased simulation speed is achieved by replacing the fully functional design sign-off model or RTL processor(s) in the design with a processor support package (PSP) based on a vendor-supplied processor model that runs faster than RTL.

• Seamless Seamless enables users to debug hardware/software integration issues early in the design cycle by running embedded software on a simulation model of the embedded hardware.
• Questa Questa is Mentor Graphic's Advanced Verification Environment and is the only integrated verification platform that can improve quality, productivity, and predictability for any verification flow.
• ModelSim ModelSim combines high performance and high capacity with the code coverage and debugging capabilities required to simulate larger blocks and systems and attain ASIC gate-level sign-off. Comprehensive support of Verilog, VHDL, and SystemC provide a solid foundation for single and multi-language design verification environments.